Hi,
Need some help of following scenario.
I have DDR3 memory connected to FPGA (stratix iv).
and the DQ and DQS driven by memory (Read) are center aligned at the DIMM.
However in FPGA at the input of DDIO macro i see DQS leading by about 6 ns to DQ.
My DDR CLK is 50 Mhz.
I am unable to constrain the relative delay between DQ and DQS (the way I used to do in Xilinx using offset in constraints).
I always see last DQS edge(falling) being missed by the DDIO.
Can somebody provide insight on exact constraints I need to put in to get DQ ahead of DQS so the data will be sampled correctly.
Thanks
Alteraguy1
