Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19328 Discussions

DE1 board to PC communication

Altera_Forum
Honored Contributor II
2,454 Views

Anyone knows how to communicate the de1 board to PC ?? for example: I need to send a data from my pc to de1 board, and make maybe a logic operation (or something), and after, receive the result data in my pc, There is a software tool to make it ? any idea? 

 

Thanks.
0 Kudos
15 Replies
Altera_Forum
Honored Contributor II
647 Views

there is a way for accessing JTAG UART from a C program using cygwin and the dll jtag_atlantic.dll.  

 

This demo has an example of the proposed approach. 

 

 

http://www.nioswiki.com/exampledesigns/highspeedimagedownloaddemo
Altera_Forum
Honored Contributor II
647 Views

That link now redirects to a wiki home page, but no longer to whatever was intended.  

Using search terms like "jtag uart" and "jtag_atlantic.dll" I can't find the page you were trying to refer to.  

 

Does anybody know how to communicate with the design inside a DE board from a C-program on the PC (running Linux on the PC).  

 

I would like to have a "reasonable" communication speed. I consider 1 Megabyte per seconde "reasonable" and 0.5 megabyte per seconde "acceptable".
Altera_Forum
Honored Contributor II
647 Views

this should be the demo referenced above: 

 

http://alterawiki.com/wiki/high_speed_image_download_demo
Altera_Forum
Honored Contributor II
647 Views

The included libjtag_atlantic.a doesn't work for me under Linux, but I'm guessing the $(QUARTUS_ROOT)/10.1/quartus/linux/libjtag_atlantic.so will do.  

 

Thanks!
Altera_Forum
Honored Contributor II
647 Views

How about simply using a serial interface and a flip-flop to make your logic operating?:)

Altera_Forum
Honored Contributor II
647 Views

I am trying to design a PC to DE board communication/control interface. I have found that the jtag_atlantic.dll can be used from the PC side to talk to the jtag_uart on the FPGA side. However all the system samples using the jtag_uart include a NIOS processor to handle the communications on the FPGA side.  

 

I have designed a state machine instead that is supposed to respond to the jtag_uart Irq events. In this way I hope to achieve a fast response an a small implementation. I have built a small C++ application which is based on the terminal example for the jtag_atlantic dll which detects the USB blaster and sends a character string to the FPGA. The USB LED on the DE board lights up each time I send a string from my utility - so a signal is getting to the board.  

 

Unfortunately - I cannot detect any Irq events from the jtag_uart (in my state machine I set up an LED to light up when Irq goes high as a debug signal).  

Because the control app on the PC used the USB blaster I can't use the logic analyzer to debug the signals in the FPGA. 

does anyone have ideas how to solve this problem?
Altera_Forum
Honored Contributor II
647 Views

OK - problem solved!!! - Altera DE boards can communicate two ways with a host PC over the USB blaster cable without a NIOS processor!!! 

 

My solution uses the Jtag_atlantic library supplied with the Quartus software on the PC side as a DLL to be pulled into the PC GUI code (C++ in my case). The jtag_atlantic.dll library can communicate with the Altera USB Blaster device driver.  

 

On the FPGA DE board I implement a Jtag_UART component and my own State_machine VHDL component which controls of the Jtag_UART, handles initialization and reset, reads and sends strings of data from/to the read/write FIFO's of the Jtag_UART respectively. 

 

Implementation is very small in terms of FPGA resources and since it is a hardware module it functions concurrently without slowing down the other functionalities in the design. As a result my implementation is based on a polling hardware solution on the FPGA side - since it is a dedicated state machine for this purpose only - the IRQ signal/service is not necessary. Although it is odd that they are not generated when enabled. 

 

One word of caution regarding this approach - since the USB Blaster is being used - it interferes with the Quartus Signal Tap logic analyzer functionality - After all both use the same USB cable at the same time. I found that the STP works fine if I do not send or receive messages during capture time.  

:) :) :) :)
Altera_Forum
Honored Contributor II
647 Views

Hi Dgabbay, 

 

i am also trying to communicate PC and DE board but i have DE2 board but didn't succeed till now. Can you please guide that this technique is also valid for DE2 board and also from where i can get this jtag_atlantic.dll library, as i have DE2 cd. Also more guidance will be appreciable if you share. 

 

Thanks
Altera_Forum
Honored Contributor II
647 Views

Hi saadip,  

I have no reason to believe that the method I used is in any way limited to a particular board design.  

 

Jtag_atlantic.dll is in your Quartus installation folders ...\altera\quartus\bin 

You will need the header file for your C++ compiler - I found one in this forum that works for me well under the name my_jtag_atlantic.h which contains the declaration of the public functions in the dll that you need. I attached the original file here. 

 

If you are working in MS VC++ on your host - I can send you the test code that I used.  

As for the FPGA side - its a bit tricky to figure out the actual mode of operation of the jtag_uart component. The documentation is not clear and I ended up using STP to figure things out. The FPGA system Qsys is attached for you. The StateMachine does all the housework for the UART and reads null terminated strings "test" in the screen shot, and responds in kind "OK" 

I hope this helps.
Altera_Forum
Honored Contributor II
647 Views

Hi, 

What task has this finite state machine? And to start your application what do you have to do on your host side? I mean...have you created any commands that you send to fpga to do something?
Altera_Forum
Honored Contributor II
647 Views

The state machine fills in for the NIOS core that Altera recommends as the manager for the Jtag Atlantic interface through the USB port to a PC host application. The NIOS core is an Altera IP and has cost which include limitations for use and distribution attached. The state machine solution is a small footprint solution free of IP limitations. 

 

On Host side you need to open the Jtag atlantic connection and then you can send ascii strings to the DE board or read strings that the board sends you back. These strings can be command strings etc. I provided the FPGA side and PC code example (vhdl, and C++) for command parsing and for sending responses back to the host with some examples.  

 

Each user can make up his own set and direct the FPGA hardware accordingly. I have a more specific version for one of my FPGA applications. It can set some memory address lines, read status lines (to augment the on-board LEDs and perform other control functions.
Altera_Forum
Honored Contributor II
646 Views

Hi dgabbay, 

 

I'm also looking for a simple solution to communicate to fpga over the usbblaster without using a nios II and found your thread. Would you provide some example code of your solution ?
Altera_Forum
Honored Contributor II
647 Views

I also wanted to establish a communication channel between board and PC without NIOS II. I was able to use the two following two methods 

  • RS-232 with about 100 kbit/s 

  • A simple output pin connection to a Labview board with 1Mbit/s * number of pins used  

 

The second one is a good option if you have a Labview board at hand. 

How fast does your communication need to be?
Altera_Forum
Honored Contributor II
647 Views

Hi stedu,  

I posted the FPGA and PC codes on: http://savant.co.il/business_downloads.html under the download link: 

"FPGA State Machine based jtag_uart communicates over USB jtag cable" 

 

I use this link as a slow command interface but as other jtag_atlantic examples show, it can be designed as a fast data link too. 

 

enjoy  

(http://savant.co.il/downloads/fpga_pc_usb_interface.rar)
Altera_Forum
Honored Contributor II
646 Views

@Pavid 

 

It doesnt need to be quick communication. Its just for configuring some hardware registers on a fpga core by using windows software. I already got two ways to do this. One with a RS232 and another one with tcl-script which i start from the software. I'm not very satisfied with the script solution, but that way doesnt need any more cable for the fpga. So i was looking for something like a .dll which i can directly use. But the only known API seems to be the jtag_atlantic.dll which can just communicate with the JTAG-Uart. 

 

@dgabbay  

 

Thank you for the code :). Check that right now!
Reply