DPA Functionality on LVDS Receiver Block

[Altera_Forum]

Hi, 

 Does each channel of LVDS serial data input has the its individual DPA block? As far as I am concerned, DPA will take in the serial data and the optimum clock phase from PLL to compensate for the skew. But if a design consists of multiple channels of serial input, say 8 channels, do these 8 channels of serial input has its independent DPA or there is only DPA which will work in such a way that DPA assumes all the serial data inputs from 8 channels are in phase and select an optimum clock phase from PLL?  Thanks, -Carid

[Altera_Forum]

DPA is working for individual input channels, allowing to compensate any kind of delay skew.

[Altera_Forum]

Thanks. So DPA block is the same as data alignment block in which both are working independently for each channel to compensate the skews induced by the input serial data and source synchronous clock while data alignment block is used to compensate the skews among all input channels. Correct me if I am wrong.

[Altera_Forum]

I don't know to which FPGA functionality you are exactly referring with "data alignment block". I'm not aware of the term used in Altera product documents. 

 DPA is only available with some FPGA families. It's usability also depends on specific protocol properties.

[Altera_Forum]

I was actually referring to one of the Altera megafunction which is altlvds receiver, the Deserializer...

[Altera_Forum]

The DPA functionality is controlled by the ALTLVDS_RX MegaFunction for those FPGAs that have it. Please refer to the lvds serdes transmitter / receiver MegaFunction user manual.