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I use cycloneV chip (se, 5CSEBA2U23C8S)) to design a transceiver, FPGA clock input is used clk0p, can not be synthesised, the following error message.
11661 Design uses HSSI PLLs that are not supported in the seleted device. 11666 Device "5CSEBA2U23C8S" does not support "Channel PLL" For this error, I tested, the cascade clock, use FPLL there are mistakes, what should I do?thanks- Tags:
- transceiver
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