Distinguish the pulse issue

[Altera_Forum]

Hello all: 

 I have a question about the pulse check issue. In our system, there will receive about 32 trigger signals. After receiving these signals, FPGA need to judge whether there are pair trigger signals' arrival time difference within 8ns. How to implement it in FPGA?!

[Altera_Forum]

I assume you've never used an FPGA before. It's difficult to answer your question in detail unless you have some FPGA knowledge but we'll give it a shot. 

 So is there just one trigger input to the FPGA? A single pin? Or are there 32 separate trigger inputs? And what is the voltage of the trigger signal(s)?  Jake

[Altera_Forum]

Hello Jake: 

 There are 32 signals input the FPGA, so the FPGA uses 32 pin receiving these 32 signals. The voltage is LVTTL. What I want to do is that picking 2 of these 32 signal randomly and judge whether the difference of these selected 2 signals' arriving time is within 8ns or not?!

[Altera_Forum]

I understand, that you're designing a coincidence detector. 

 It can be done with an FPGA, but there's one restriction. The timing measurement must use a discrete timing, so the 8 ns criterion can't be checked exactly. Depending on the FPGA family, a timing resolution of e.g. 1 or 2 ns can be achieved with accetable effort.

[Altera_Forum]

So, there are a couple of ways you can do this. To satisfy the Nyquist criteria you need at least a 250Mbps sampling rate. However, I think you'll want to get the resolution of the samples as high as you can. Here are two options: 

 1 - Run the sampling clock as high as you can and use double data-rate I/O to double the sampling rate. So for example, if you run the FPGA clock at 500MHz (this can be done in Stratix II or higher), then use the DDIO inputs of the registers to get an effective sampling resolution of 1ns. You can then do some simple comparisons to see if two pulses occurred within 8ns.  2 - If you are going to use a slower FPGA with a slower clock, use a PLL to create multiple phases of the clock. So if you run the clock at 200MHz with 5 equally spaced phases, you also get an effective 1ns sample resolution. You'll need to do some clock resynchronization and you'll want to manually place the input registers to assure minimum skew between the samples.  3 - You could simply run at the minimum 250Mbps sample rate. Obviously your chance of error increases.  Jake

[Altera_Forum]

Hi both： 

 Thanks！

[Altera_Forum]

Hi Anyone: 

 The single event's resolution is not a problem. But, there are many continously events coming, and how to do these TDC events?!

[Altera_Forum]

Your specification isn't clear. "continously" can mean a lot.