Does the jic file in flash play a role in the download process of the sof file

[WhittierChen]

During the test of our products, we found that the FPGA did not work properly. We downloaded a SOF file on the FPGA under the test environment and found that the NIOS software program started normally. Would you like to answer whether the ELF file generated by NIOS in the JIC file will be re-read after the SOF file is downloaded, or the ELF part will be read into the SRAM of the FPGA when the FPGA is powered up? Hope to reply as soon as possible. This is very important for us to eliminate the fault! Thank you very much indeed

[KellyJialin_Goh]

Hi,

Greetings and welcome to Intel's forum.

Here are some relevant information on your queries:

To generate .jic programming files with the Intel® Quartus® Prime software, you must first generate a user-specified SRAM object file (.sof), which is the input file. Next, you must convert the .sof to a .jic file using the Convert Programming File dialog box.

To integrate a NIOS II software project executable ELF file into a Quartus II hardware project SOF file, you may refer to this video for further information: https://www.youtube.com/watch?v=joFaxLY-rUE

Hope this could clear your doubts.

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

Any updates from your side? Are there any further clarification needed from my end?

Hope to hear on your findings.

Thank you.

Regards,

Kelly

[WhittierChen]

No, I know how to generate jic files. As you know, using nios requires the .elf file generated by nios in the process of generating .jic files. I want to know whether the .sof file generated by pl and ps after compilation includes the .elf file compiled in nios? If not, after the .jic file has been downloaded into the flash, power up the FPGA, and then download the corresponding .sof file. Will the part of the nios program in the .jic file be read from the flash?

[KellyJialin_Goh]

Hi,

I am afraid the elf file and sof file are separated and elf file will not be read when it is downloaded to the FPGA.

May I know the quartus version and Development kit that you using?

You need to have an EPCS flash controller in your SOPC design. Then you need to set the reset vector of your NIOS to the EPCS flash.

In order to write your sof and elf to flash you have to use Nios Flash programmer or Nios flash programmer command line with the link attached here: https://www.intel.com/content/www/us/en/docs/programmable/683118/current/overview-of-the-flash-programmer.html

You may also refer to this link for additional information:https://www.intel.com/content/www/us/en/support/programmable/articles/000081656.html

Hope this could clarify your doubts.

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

Any updates from your side? Do you need any further clarification from my end?

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

Just for your information, for nios, the .jic is usually contains .sof + your application , as the new .sof usually will have a .hex included in the Quartus design to be recompiled again.

Hope this could clarify your doubts.

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Thank you.

Regards,

Kelly Jialin, GOH