EPCS16 AS Can't Verify Device (General AS Programming Issues)

[Altera_Forum]

I have a custom board and the TerasicBlaster (USB Blaster Clone) and at least some communication seems to start OK (reports Device 1 silicon ID is 0x15). I can Erase and Blank Check successfully most of the time (have had a few errors). But when I program and verify it goes through what appears to be the programming process for maybe 15-30 seconds, and then says Can't verify device 1 immediately after trying to starting verification. I'm totally new to this FPGA stuff, and any pointers would be much appreciated! 

 Thanks!  -JNS.

[Altera_Forum]

I expererienced similar behaviour with USB Blaster and a 0.5 m long IDC flat cable that worked correct for JTAG programming. With a regular short cable, AS programming proceeded normally. You are probably using the Terasic USB Blaster with it's original cable, so you have no option to further improve AS signal quality.  

 You can see however from my experience, that AS programming interface is rather sensitive to signal quality issues, more than JTAG. With Cyclone III, Altera published a suggestion to connect a small capacitor (around 10 pF) at DCLK which apparently improved the situation. Also a small series resistor at DCLK (50 - 100 ohms) may help. I assume, that AS programming connector and EPCS are located near to FPGA and have state-of-the-art wiring, otherwise, the problem could be related mainly to your design.  It could be, that although verify fails, the device is programmed correct. If you have also a JTAG interface at the FPGA, you can program the AS device through serial flash loader (SFL) alternatively. SFL works with all FPGAs that also support SignalTap. See the respective application note how to use SFL.

[Altera_Forum]

Thanks for the ideas. I have 10pF on DCLK, but I'll try some different values and experiment with the series R. 

 How involved is the FPGA in the process during the programming of the configuration device? Is it being programmed simultaneously and signaling back to the usbblaster. Is the Usbblaster trying to verify from the epcs chip or the fpga?  Off to do some experimentation.  Thanks, -JNS.

[Altera_Forum]

The FPGA isn't involved in AS programming, the FPGA AS interface is disabled by the USB Blaster or another programmer, as it pulls up the nCE line. AS Programming would be possible without a FPGA assembled to circuit. 

 But the FPGA can also program AS memory through the interface, this is utilized with said serial flash loader.

[Altera_Forum]

--- Quote Start ---  The FPGA isn't involved in AS programming, the FPGA AS interface is disabled by the USB Blaster or another programmer, as it pulls up the nCE line. AS Programming would be possible without a FPGA assembled to circuit.  But the FPGA can also program AS memory through the interface, this is utilized with said serial flash loader.  --- Quote End ---    Just to be sure, is this true for the whole program + verify cycle? What I'm thinking here is that if it is, then I need to focus on the Rs and Cs between the AS connector and the EPCS for now, get that working, and only then concern myself with the connections between the EPCS and the FPGAs? I have jumpers installed between the EPCS and the FPGAs, so I could even take them completely out of the picture for now if that might help (Right now I only have one FPGA installed on the board BTW).  Thanks!  -JNS.

[Altera_Forum]

Another question. Should the silicon ID be 0x14 or 0x15? I get both at different times, and it would be helpful to know which is correct, if either, but I'm not finding any authoritative info online. 

 Thanks, -JNS.

[Altera_Forum]

--- Quote Start ---  The FPGA isn't involved in AS programming, the FPGA AS interface is disabled by the USB Blaster or another programmer, as it pulls up the nCE line. AS Programming would be possible without a FPGA assembled to circuit.  But the FPGA can also program AS memory through the interface, this is utilized with said serial flash loader.  --- Quote End ---    OK, a step in the right direction thanks to this info. I pulled all of the jumpers connecting the EPCS to the FPGA circuit and now the EPCS programs and verifies properly. So I think I will move forward by replacing the previous 0Ohm jumpers with small resistors and see what I find.  Just wanted to give the latest update in case it inspires any ideas on someone else's part.  Appreciate your time and help.  -JNS.

[Altera_Forum]

EPCS16 silicon ID is 0x14, as documented in the configuration handbook. When even the silicon ID is read incorrect, some serious hardware problem seems to be present. Do you have any additional components connected to the AS interface or a supply voltage different from 3.3V?

[Altera_Forum]

My supply voltage is 3.3V, but when I was getting an occasional 0x15, I had some fairly long lines that extend out to the pads that will hold the other FPGAs attached with no series resistors or caps.  

 I had a bit of other work to do, but right now I'm going to start connecting those other lines through resistors one by one to see if it works, and if it doesn't, try to isolate the problem.  Will update with the results.  Thanks for the info!  -JNS.

[Altera_Forum]

I didn't notice from your previous posts, that you apparently are using a AS to multiple FPGA configuration scheme. I wonder what's the exact circuit your using in this case, cause I didn't find an Altera circuit example with multiple FPGA and AS programming interface.  

 It is necessary to connect the nCE pin of first FPGA to the programming connector as in the single FPGA circuit, otherwise any of the connected FPGA could drive out DCLK or DATA line, conflicting with the programming adapter.  If the circuit as such is correct, it could be a problem of, as you said, fairly long lines, but I didn't use multiple FPGA AS configuration yet and don't have experiences on my own regarding this matter.

[Altera_Forum]

Right, the eventual intention is to program multiple FPGAs. Right now I only have one chip installed though. The DATA and DCLK are buffered right after the first chip (buffers not yet installed either), and I do believe that I have the nCE connected correctly (the first one is connected to the header, the others will be tied to ground when the chips are installed). So for now what I have is essentially the standard single chip AS design. 

 I've gotten the EPCS device to program+verify semi-consistently (sometimes it takes a retry or two - seems to be at least partially related to the orientation of the IDC cable coming out of the TerasicBlaster), by putting 25 Ohm resistors in series on all the lines between the EPCS and the FPGA, so that's at least a step forward. Now though I'm trying to get the FPGA to configure, and nothing happens. I don't see any activity on any of the lines from the FPGA to the EPCS. They just sit in the following states (this is with the AS connector disconnected):  Do -> High nCS -> High CONF_DONE -> Low nCONFIG -> Low DCLK -> Low nCE -> Low with a bit of noise (about 275mV Pk-to-Pk @ around 400Hz) DATA[1] -> Low nSTATUS -> Low  I also just noticed an oddity. With the board unpowered, I'm reading ~0 Ohms from CONF_DONE to ground with my normal multimeter. Is this typical? The PCB hasn't been electrically tested, so I can't confirm that it's not a fab error with the board (although this is unlikely, as I CAN confirm on a fresh, unpopulated copy of the board that it's not a design error).   Even if there were a problem with my design, the FPGA should be at least trying to configure, right? And if not succeeding, it will just keep retrying?   It seems that it's a real possibility that the FPGA has been damaged and that I should try replacing it. Unfortunately, I seem to be out of my ChipQuik removal solder and have no good way to remove the FPGA until getting more, so I may just have to try rebuilding the whole thing on my bare board in the meantime.  Going now to reread the configuration section of the Cyclone3 Handbook, and possibly start rebuilding the circuit on my 2nd board. Appreciate any thoughts you may have.  Thanks, -JNS.

[Altera_Forum]

I don't know what's happening with your circuit. A strange thing is nCONFIG being permanently low, cause it's an input to the FPGAs. However, if it's low, no FPGA can start configuration. I would try to clarify this first. Also I would not start desolderig parts before all other options have exhausted. 

 Good luck!

[Altera_Forum]

Thanks for the reply. I'm trying again on my 2nd board just to see if anything becomes apparent. I had a little difficulty soldering the FPGA because while I'm used to soldering QFPs these leads seemed more delicate than I'm used to. Things seem to be going better soldering it this time around. I also built the EPCS circuit first, since I know now it can be programmed on its own at it worked first time.  

 Have my fingers crossed - will keep you posted.  -JNS.

[Altera_Forum]

Ok, I haven't had a chance to investigate the why, but my second board works, at least with the first FPGA. In another thread before getting the boards fabbed I was in a discussion also about whether or not my design would work with 128 simultaneous channels of 1MHz PWM, and that seems to be fine. I still have a lot of hurdles to jump before getting this thing finished up, but this is a huge start. 

 Thanks for all your help, and I'll be back posting more progress (and probably questions) as I keep moving forward.  -JNS.