Error in Intel Cyclone 10 Design

[ericmtzr]

Hi,

one of my clients is having problems when he tries to use a global clock, I attach an image with the error.
Could you please help me?

[RichardTanSY_Intel]

CAUSE: You assigned a pin to a location that is not connected to the specified port type of the specified fast PLL or enhanced PLL . As a result, the Fitter cannot place the PLL.

ACTION: Change the location assignment for the I/O pin or delete the assignment.

[RichardTanSY_Intel]

I believed I have answered your question.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[ericmtzr]

The board has been laid out and the 100MHz FPGA system clock (CLK_SYS) is unfortunately connected to pin AA3, so we cannot change the location for the I/O pin at this point in time.
Could you recommend some other workaround?

[ericmtzr]

Hi, 

Do you have any option?