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Error when load "final" snapshot for multipal partitions

xaoyaolee
Beginner
349 Views

Quartus Prime Pro 13.0, Stratix 10. 

 

Our design is too large, so that we use block based design flow.

There are four core partitions in whole design. We floorplan the four partitions with logic lock region(Fixed/Locked),   they have space between with each other, so they are not overlap.

We use four different projects which include each one partition to produce snapshot of each partition. 

Compile and extract the *.pdb file correct.

But when the consumer import the four *.pdb file into the project, quartus report error like this:

"The routing element at location "R24_C16_INTERCONNECT_DRIVER_X66_Y219_N0_I0" is being sourced by routing elements at locations "R24_X53_Y219_N0_I85" and "R4_X63_Y219_N0_I24
.  This can be caused by improting two or more preserved partitions with overlapping routing or global signals."

I checked the four partition's shape and location. Found that the core logic of partiton is a little beyond the logic lock region, so maybe they overlapped with each other.

 

I try to remove two partiton, so the space of existing two partition is very large. And above error disappears.

 

So my question is: how to control the complier strictly constraint logic NOT beyond the logic lock region?  

 

 

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9 Replies
tventing
Employee
301 Views

Hi,


Can you attach the project .qar file?

I will need to investigate your design to get back to you regarding this issue.


Let me know if your design is open to public. If no, I can approach you through email.


Thanks.

Best Regards,

Ven Ting



sstrell
Honored Contributor III
289 Views

I'm presuming you mean ".qdb" files, not ".pdb" (don't know that is) and that you are using a more recent version of Quartus than 13.0 (there was no Pro edition of Quartus back then).

Anyway, the error sounds like it's not specifically an issue of resources physically in the LL regions.  LL regions restrict resource placement into regions like LEs, memory blocks, and DSP blocks.  Routing wires and clock signals have separate rules and requirements and using the final snapshots from the reused designs may have added restrictions that caused the error.

Can you use the synthesized snapshot .qdb file from the other projects (the developer projects as they are named in the documentation)?  You can still use the LL regions in the final project (the consumer project), but using the synthesized instead of final snapshot gives the Fitter freedom in the partition's placement, limited only by the LL regions.

xaoyaolee
Beginner
260 Views

I constriaint routing area with expansion 1( I don't constrint routing area before), it seems the logic beyond the LL region is reduced to little, that make helps, but makes the routing congestion bad.

Finally, I abandon the design partition re-use methodology(different partition complied by different project), but use Incremental compilation in one project, which succeed.

Compile and fitter one partition each time, mark it as "final", do the other partition at next time,  one by one. This methodolgy don't making partitions overlapped. 

tventing
Employee
269 Views

Hi,


Do you have any updates? I look forward to hearing from you.


Thanks.

Best Regards,

Ven Ting


xaoyaolee
Beginner
260 Views

Please look at my reply to other person.

tventing
Employee
212 Views

Do you still use LL to constrain the design partition before compile and fitter one partition each time and mark it as "final"?


Seems like this methodology gives the compiler more freedom to do placement and routing.


Thanks.


tventing
Employee
177 Views

Hi,


Do you have any updates on this?


Thanks.


tventing
Employee
131 Views

Hi,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thanks.

 

Best Regards,

Ven Ting


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey


xaoyaolee
Beginner
113 Views

Hi,

     I have already reply to you at 19 Sept:

 

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