F-Tile Interlaken Intel® FPGA IP Example Design External Loopback HW Test

[emrahener]

Hi,

I am using F tile Interlaken  IP on AGIB027R31BE2VAA device using Quartus 23.1. I am loading Example design generated for 12x12.5 Gbps NRZ Configuration to my custom HW and using the system console to access JTAG control as described @ https://www.intel.com/content/www/us/en/docs/programmable/683069/23-1-6-1-0/testing-the-hardware-design-example.html

I have a loopback cable on connected to  transceiver pins.

When I use run_example_design (internal loopback) the HW test pass. When I execute run_example_design_exlb    for external loopback test  after run_example_design the design stays in internal loopback mode and test again pass. 

When I execute run_example_design_exlb directly after loading sof file the design fails. I attached Signal Tap logic analyzer to some internal signals and observed that rx_usr_srst remains high.

Can you please help me with debugging the source of the problem (HW or IP related etc)?

Kind Regards

Emrah ENER

[ZiYing_Intel]

Hi,

Since the issue has been raised in the IPS, then let us just discuss the issue in the IPS. Firstly, you need to ensure you loading the .sof file successfully and I will be need some time to do the debugging of the problem from my side.

Best regards,

Zi Ying