F-Tile PMA Direct PHY - USB3 - Enable per PMA lanes TX and RX ready signal issue

[shauls]

Hello,

We are using DPHY IP configured for USB GEN1&GEN2 - Quartus 23.4

DPHY Configuration : USB , 2 lanes , Enable per PMA lanes TX and RX ready

When training link at GEN1 for 2 lanes it seems that rx_ready of second lane stay de-asserted.

 looking at DPHY IP on the following files we found the issue:

*_directphy_f_*.sv

// wire [num_sys_cop-1:0]          int_rx_ready; // Generated IP

wire [ready_width-1:0]               int_rx_ready; // Should Be

directphy_f_sip_*.sv

//.dphy_reset_status_tx_ready_i               (tx_ready), // Generated IP

//.dphy_reset_status_rx_ready_i              (rx_ready), // Generated IP

.dphy_reset_status_tx_ready_i                 (&tx_ready),  // Should Be

.dphy_reset_status_rx_ready_i                 (&rx_ready),  // Should Be

Attached DPHY IP with READY signal issue.

Just to mention that although I fixed it the RTL it is functionally not working well.

rx_ready signal of second lane fail unexpectedly and afterward rx_ready of first lane fail also.

Thanks,

Shaul

[Kshitij_Intel]

Hi,

In Q23.4 USB option and support has been removed. I opened your shared .ip in Q23.4. You are getting an error USB is not an option now. Sharing the screenshot below.

Thank you,

Kshitij Goel

[shauls]

Hello Kshitij ,

I have an *.ini file that enable USB on Q23.4.

I can send it to you by Email

Shaul