Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20792 Discussions

FPGA load on cyclone V GSRD

Shoval
New Contributor I
501 Views

Hello all,

I have done the step-by-step Cyclone V SoC GSRD (https://www.rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD)

 

After successful compilation and boot from SD card on the cyclone V EVB, seems like something is strange regarding the FPGA.

In u-boot the FPGA is successfully loaded, and the 4 FPGA LEDs turn on, at kernel boot they turn off and remain off.

in the precompiled SD card from the GSRD the LEDs turn on after u-boot FPGA load, than at kernel boot off, and during Linux initialization they start to toggle.

Also, running the demo binaries in intelFPGA directory does nothing (had error "Failed opening fifo frequency_fifo_scroll" but i digged up and there was a .intelFPGA directory missing).

 

How can I access the FPGA directly or verify it is loaded and running?

 

Labels (1)
0 Kudos
1 Solution
aikeu
Employee
477 Views

Hi Shoval,


May I know did you perform the cmd "bridge enable" in UBoot after the FPGA hardware design has been loaded?

When you open GHRD with the qsys file in the quartus platform designer. You can see the sysID(System ID Peripipheral IP) with the data of 0xacd51500 when open the parameters of that IP.

Based on the system design connections referring to the IP address assignment, you can use the cmd "md" after "bridge enable" in Uboot (md 0xFF460008) to check the expected sysID data is 0xacd51500. This will help to check the design has been loaded into the FPGA fabric through LWHPS2FPGA AXI Bridge Module(h2f_lw_axi_master) with the HPS memory address of 0xFF400000:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html


Thanks.

Regards,

Aik Eu



View solution in original post

0 Kudos
3 Replies
aikeu
Employee
478 Views

Hi Shoval,


May I know did you perform the cmd "bridge enable" in UBoot after the FPGA hardware design has been loaded?

When you open GHRD with the qsys file in the quartus platform designer. You can see the sysID(System ID Peripipheral IP) with the data of 0xacd51500 when open the parameters of that IP.

Based on the system design connections referring to the IP address assignment, you can use the cmd "md" after "bridge enable" in Uboot (md 0xFF460008) to check the expected sysID data is 0xacd51500. This will help to check the design has been loaded into the FPGA fabric through LWHPS2FPGA AXI Bridge Module(h2f_lw_axi_master) with the HPS memory address of 0xFF400000:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html


Thanks.

Regards,

Aik Eu



0 Kudos
Shoval
New Contributor I
433 Views

Hi Aik,

Seems like the FPGA is loaded, I can access the PIO directly from memory address 0xff260040 and toggle the LEDs.

0 Kudos
aikeu
Employee
410 Views

Hi Shoval,


Glad to hear that I managed to help in resolving the issue!

I am closing the thread for now. Do consider open a new thread if there is other question.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


Thanks.

Regards,

Aik Eu


0 Kudos
Reply