Handshake problem

[Altera_Forum]

Hi. I have a problem designing a handshake sistem. I think it's imposible to do it to the tasks. I must have two different clocks. For instance ck1 with a period of 7 and clock 2 with a period of 5. I must obtain the pulse signal in the draw. It must go forever. The problem is that i don't think it will work for any clocks like the specifications says. I think it will work only it the posedge or the negedge of the ck1 falls exactly when the 4 period pulse signal from the pulsegen has finished(when a posedge of ck2 will start). Do you have any sugestions on how i can make this work? Thank you!

[Altera_Forum]

I'm not sure I understand what you mean. 

If ck1 and ck2 are unrelated, i.e. without an exact phase relation, using them to directly clock the system could lead you to unexpected behaviour. You'd better use a single clock. For example, if ck1/ck2 frequencies are not so high and if you can generate extra clocks with a pll, you can create a single clock with a period of 1 and use it instead of ck1 and ck2. This approach would require minor changes in your Timer and PulseGen modules, but it would lead to a more robust design.

[Altera_Forum]

Yes, i know that. But unfortunatly these are the specifications and i can not make any hardware change. Thouse are all the signals i must have in these design. I tought mabe there is a solution i know nothing about, even i don't think this is possible.

[Altera_Forum]

Thank you!

[Altera_Forum]

--- Quote Start ---  I tought mabe there is a solution i know nothing about, even i don't think this is possible.  --- Quote End ---    Nothing is impossible (ok, let's say almost nothing...). There are a few ways to do what you need, but this depends on some unspecified details; for example: - where ck1 and ck2 come from? (external? generated from fpga?) - is there a fixed phase relation between them - what can you change and what not In the worst case where ck1 and ck2 run independently and you don't have a higher frequency clock, your signals would necessarily suffer a time uncertaintly up to the maximum among ck1 and ck2 period. This is unavoidable. You can reduce it to half by sampling on both edges, but I would not recommend this.

[Altera_Forum]

Hi, 

 try the following scheme (check attachment).  I would suggest to run sim first.  Secondly this scehme transfers only one pulse at a time, you may improve the circuit as per requirement, and finally, everything is possible , provided we dont set unreasonable constraints. In your case it looks possible.