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Hi everyone.
Just wondering how could the Altera Megacores altmult_accum help designing the time-domain correlator. It would be greatly appreciated if someone explain me the basic aspects of the design. Thank you very much. PS: my correlator design idea derived from this paper: http://img134.imageshack.us/my.php?image=correlatorbasicrf2.jpgLink Copied
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SOOOOO many thanks for your pic PARRADO. I've just got a completely new idea for my correlator, it will use much less the FPGA cores, however a bit slower.
I made a calculation: if I want to correlate 1000 samples from the ADC with 66 points reference signal, it would take (1000+66)*66 = 70356 clock cycles to complete the correlation. If a 40Mhz system clock is used, than the correlation frequency can get upto 40,000,000/70356 = 568 Hz. Is my calculation correct or not ? If it is, then 568 is fast enough. Again, thanks a lot for your help, much appreciate.
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