How to force AltPLL to use a specific PLL block.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to force AltPLL to use a specific PLL block.

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I understand that specific clock pins go to the PLL blocks.

I have to use a specific clock pin, PCB is laid out, so how do I tell Quartus to use the PLL block connected to my clock pin?

Using Cyclone III EP3C25E144I7, Quartus 11.1

The critical warning I get is:-

Critical Warning (176598): PLL "altpll0:inst21|altpll:altpll_component|altpll0_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_54"

Thanks for any help.

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