How to simulate a design created in Platform Designer System

[Sijith]

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design that is created using Platform Designer System.  I would like to elaborate a bit:  my counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and then executed "Generated HDL" and "Generate test bench" option in Platform Designer System. Also, I compiled the whole design in Quartus Prime Pro. May I know what I have to do to simulate  the whole design? (I have model-sim with my Quartus Prime Pro 18.1.). I have got this doubt since I am using  an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design. 

[sstrell]

Best is to see this training first which summarizes your options: https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true

[Sijith]

As a beginner, I felt bit difficult to follow this the training at a couple of places. I will just list what I understood and please correct me if I got it wrong. I assume BFM is basically a functionality that helps in simulation(?)

My specific case: {I have 2 blocks of IP's (we can call block A and B) in platform designer system. Block A have two IP's (IP_1 and IP_2 that connected though avalon streaming interface.  The IP_2 is having avalon MM slave port at one end (the end that connects to block B)). I have a counter in IP_1 and it streams data to IP_2 and which is a FIFO and should pass data to block B through avalon MM interface. The IP_2 and which is a FIFO have a MM read slave that connects to the read master in block B.

I just want to simulate the block A part of the design and see how the output signals from IP_2 FIFO looks like in wave form.}

1) I assume I should follow that sl.no- 29 to 34 in the video. I built a system in the platform designer and I have exported clock and reset to IP_1 which are only input to my design for block A. Also, I have the avalon MM slave port from IP_2 (which is the output from the design of block A). I assume I have to export it in platform designer?

2) Generated testbench system and selected "simple BFM's for clock and reset" . And I have got a _tb.qsys file and got simulation files in _tb folder. Opening _tb.qsys file, I could see clock_bfm and reset_bfm components in platform designer connected to the DUT (for me design of  block A). 

3) I think I have stuck at how to write test program for my specific case (or its created during the test bench generation?)?  Any suggestion? Unfortunately the video regarding this did not help me to comprehend much.

I assume I have to follow same  procedure as (?) in sl no. 19 in the video (single IP example) for the combined design also. In sl no. 19 (Avalon MM interface BFM Read/Write operations for Verilog)  ( here, I assume in my particular case I should use "Read" option).  I did not understand `define MSTR_BFM mstr_test_prog.mstr_bfm_top.mastr_bfm .  May I know "mstr_test_prog" is the name of the test program means? (how this name appears?--is it project name?).  I assume the .qsys file used is  mstr_bfm_top.qsys ? (or it has any other significance?). Also, from where we gets BFM instance name?

Also how we are getting the set_command_<X> (Y) . How we decide what are the things to use in the place of X and Y in the for loop?

Thank you very much.

[ShengN_Intel]

Hi,

This video and this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/133550/ will show you how to simulate ip in Quartus Prime Pro Edition. First in Platform Designer, you have to generate the simulation model. Next after full compilation, have to generate combined simulation setup script for IP. Then create a .do file to source the combined simulation setup script and also compiled all the related design files, testbench (Note: testbench need to be created as well). Last, execute macro to run simulation.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[Sijith]

I assume the method in the link above works for a design containing multiple IP's (not just one IP) connected with avalon interfaces (streaming and MM). I am afraid that I could not comprehend well 3:40 of the video posted (In the documentation, 

"vlog <compilation options> <design and testbench files> Add command to compile all user design files and testbench files except​ ​IP design.)

the testbench files and design files here means the .v files in the "Project Folder/projectname_tb/" folder? And design files from "Project Folder/ip/projectname/projectname_ipcomponent folder/synth" and "Project Folder/projectname/synth" folder ? Also, "except IP design" in above quote means .v files of IP's or .ip files?

My doubt is whether the user have to write some code additionally (like the testbench toplevel module "tb" mentioned in the video, or we just have to collect all necessary codes from different folders (that created while executing "generate testbench" option?) and add them in <design and testbench files> entry in the .do file?

[ShengN_Intel]

Hi,

Since your design only involved IP. In platform designer Generate HDL GUI, if you have enable the Create simulation model under Simulation section, there should be Project Folder/Qsys_system_name/sim folder generated.

The design files mean the .v files in the Project Folder/Qsys_system_name/sim folder. And source the simulation setup script (msim_setup.tcl) in the Project Folder/Qsys_system_name/sim/mentor folder. Yup, "except IP design" in above quote means .ip files.

Yup, user have to write testbench additionally. Check this link https://www.intel.com/content/www/us/en/docs/programmable/683305/19-4/simulation-quick-start.html for example design download.

Check this also https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/specify-files-for-simulation-in-the.html

To support Platform Designer system generation for your custom component, you must specify VHDL or Verilog simulation files. In most cases, these files are the same as the synthesis files. To use your synthesis files as your simulation files, click Copy From Synthesis Files. 

Thanks,

Best Regards,

Sheng

[Sijith]

Thank you for sending the example codes! 

I still have a couple of doubts and great if you could address them.

1) May I know what "Project Folder/Qsys_system_name_tb/" used for? (which have ip and Qsys_system_name_tb in it )and created in it after generate test bench in platform designer. Also does the "Project Folder/Qsys_system_name/synth"  file contains design files? Sorry I have a hard time to understand it.

2) From your last message-- "The design files mean the .v files in the Project Folder/Qsys_system_name/sim folder." .v file, you meant system verilog, right? (I could locate an .sv file in that folder even if I opted for verilog in simulation option inplatform designer Generate HDL GUI)

3) And I assume "Project Folder/Qsys_system_name/sim" contains the .v or .sv files created by Quartus Prime Pro and is optimized for the simulation?

4) I also have a basic question too, I know when we use the system builder tool is used to get a design and a toplevel .v is created. But when we use the Platform Designer system to design a system, is there tool that automatically generate a top-level module? or we have to manually create a top-level  .v file and instantiate the .v file created in "Project Folder/Qsys_system_name/synth" during "Generate HDL" process in the Platform Designer? 

[ShengN_Intel]

Hi,

"Project Folder/Qsys_system_name_tb/" is for BFM which is the ip in platform designer under category Basic Funtions -> Simulation; Debug and Verification -> Simulation and also need further the test program to simulate.

"Project Folder/Qsys_system_name/synth" is the files for synthesis. "Project Folder/Qsys_system_name/sim" is the files for simulation. Both path folders should contain the same top-level wrapper .v files if you opted for verilog in simulation option in platform designer Generate HDL GUI. Have you do like this for custom ip https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/specify-files-for-simulation-in-the.html? Is just "Project Folder/Qsys_system_name/sim" got simulation setup script .tcl compared to "Project Folder/Qsys_system_name/synth". May be you can try with one Intel ip and see.

Thanks,

Best Regards,

Sheng

[Sijith]

Thank you for your reply.

Yes, I have used the VHDL simulation file same as the synthesis file (counter.v) while developing the custom IP.

I assume you were asking about the _hw.tcI file (related to the custom component)? . Also, I can see a msim_setup.tcl file in Project Folder/Qsys_system_name/sim/mentor (Assuming it contains setup script for the simulation for the entire design?). I am attaching the _hw.tcl file with this message.

I am  attaching a compressed version (.zip) of my Project Folder. The  counter.v is my verilog code for counter component and is used to make the custom IP counter_module. 

1) Is it mandatory to have a user-defined Top-level HDL file of the design in the Project Folder (something like .v file created by Terasic System Builder tool, in the Project Folder of DE5a-NET-DDR4 example designs)? . I am bit confused as this project compiled without a user defined top-level module. But I thought that setting counter_fifo.qsys file as top-level entity worked as it includes the /Counter_FIFO/counter_fifo/synth/counter_fifo.sv (Please refer attached image Capture.PNG) . The files included in my Quartus project is screenshotted and attached as Capture.PNG

2) May I know the  .sv file in Project Folder/Qsys_system_name/synth will have the similar role of  PLL_RAM.v in the example design you sent me  https://www.intel.com/content/www/us/en/docs/programmable/683305/19-4/simulation-quick-start.html here. 

3) Since my  Project Folder/Qsys_system_name/sim/ folder contains only one .sv file, I assume my Project Folder/Qsys_system_name/sim/mentor/msim_setup.tcl file should include this file only, right? or am I still missing something?  (I mean just this line, vlog -vlog01compat -work work C:/Users/abc/Desktop/Counter_FIFO/counter_fifo/sim/counter_fifo.sv) 

4) Then I assume I need a testbench file similar to that in the example sent by you, to simulate my coustom IP + IP design?

It would be great if you could point the "user design files and testbench files" needed to source in the msim_setup.tcl in this case. It would be helpful for me to comprehend it well.

Thank you.

[ShengN_Intel]

Hi,

1) Setting counter_fifo.qsys file as top-level entity should be enough. ../Counter_FIFO/counter_fifo/sim and ../Counter_FIFO/counter_fifo/synth contain the same auto-generated .sv file so I think you can treat that .sv file in ../Counter_FIFO/counter_fifo/sim as top-level module. The Top-level HDL file of the design had been auto-generated.

2) Yup, .sv file in Project Folder/Qsys_system_name/synth will have the similar role of PLL_RAM.v in the example design. But since you're going to run simulation, have to use the .sv file in Project Folder/Qsys_system_name/sim.

Attached the zip file below. Check the do file sim.do in ../Counter_FIFO/counter_fifo/sim/mentor and example testbench counter_fifo_tb.v in ../Counter_FIFO/counter_fifo/sim. In do file, need to source the setup script msim_setup.tcl in sim/mentor then vlog both the top-level module counter_fifo.sv and example testbench counter_fifo_tb.v. Run the macro do file, you'll get the waveform like the picture attached below.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[Sijith]

Hi,

Thank you very much for helping me out. I have a couple of questions.

As I have simulated my counter.v and with the testbench (please refer Counter_FIFO/counter_tb.v). The screenshot of the simulation wave I got is attached Capture.PNG. 

I am just wondering that why I could not get the same output from the counter_fifo module's output port "out_readdata"?

In short, I would like to verify that  the output from the counter_fifo module is same as the output from the counter module  which counts upto say 100 (because counter_fifo is a combination of counter and FIFO modules. And counter module is supposed to feed data to the FIFO and have to get out put though the FIFO output). 

What are the modifications I have to do in  ../Counter_FIFO/counter_fifo/sim/testbench counter_fifo_tb.v  or some other files to get the similar counter output through the counter_fifo module? or this something out of scope of the simulation?

[ShengN_Intel · Accepted solution]

Hi,

The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.

Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.

Thanks,

Best Regards,

Sheng

[Sijith]

Thank you very much and much appreciated your help.

I have a question, as a contributor mentioned about the use of BFM : https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true to simulate the Platform Designer generated design.  If that is also a recommended solution, could you please address the question I wrote on 05-23-2023   (please click on this date for the link to message).

I have a completely different question too in one of your comment you said "Since your design only involved IP".  I am afraid that I did not get it well. Is there any possible other scenario like, designs with IP's + VHDL module component (not converting to custom IP) in a project? If so how can they get connected in a project. I assume that the Platform Designer only supports connecting between IP's (off the shelf or custom built)?

Thanks again.

[ShengN_Intel]

Hi,

Check the design zip file qwork1.zip attached and document inside the zip file. Check also this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-avalon-verification-ip.html for example design and pdf. Probably you'll have better understanding on BFM and test program. The test program is similar and applicable to the question 3) you wrote. `define MSTR_BFM mstr_test_prog.mstr_bfm_top.mastr_bfm this define the Master BFM id in platform designer. The set_command_<X> (Y) you can find in the pdf.

For IP's + VHDL module, you have to instantiate the IP's top module (in your case counter_fifo_inst.vhd) in VHDL module in order to connect them. Then the combined simulation setup script is needed like this video link posted before.

Thanks,

Best Regards,

Sheng

[Sijith]

Hi Thank you very much!

I have noticed that when I simulate just counter module (using counter_tb.v, that I attached in earlier message)  the wave form of the data output (avalon_data) behaves as normal (have starting value 00000000000000000000000000000001) and starts the data with 32b'1 (please see attached Capture_wave_counter.PNG). But at the same time, when I simulate the counter_fifo with the testbench counter_fifo_tb.v . The fifo_0_out_readdata looks something different than the  and the first entry is `00000001000000000000000000000000` (looks like counting started from the 8th bit. Please see the picture Capture_wave_counter_fifo.PNG). Also please see Counter_fifo_wave_1.PNG

Is it something to do with the FIFO parameter setting? You can see from the Counter_FIFO/counter_fifo.qsys file the parameters I used (also see the attached counter_fifo_qsys.PNG). I am just wondering that setting channel width parameter =8 in Avalon-ST Port settings of FIFO IP has to do something with this? (as you can see in counter.v, there is no signal named "channel" defined in it). I read from the FIFO IP manual that 'channel" signal is not mandatory one, and would like to make sure that the did not make any difference here.

I am wondering that whether  is still missing?

Thanks again!

[Sijith]

Hi Sheng,

Recently I have got a mail from Intel community that suggesting to open a new thread.  If I want to raise my latest question as a  fresh case, I am afraid that I may have to summarize the whole discussion here the new thread too.  Is there any other way to circumvent this?