How to transmit video data to DDR and display ?

[2258432]

Hi all,

I have used the test pattern generator II IP in Platform Designer to generate video data and connected its dout to the din of the clocked video output II IP. Finally, I output the video to HDMI, and this approach obviously displays the video.

Now, I want to use the MSGDMA to move the video data to DDR3 first, and then use another MSGDMA to read the data out to the clocked video output IP for video display. However, the video cannot be displayed, and the HDMI signal is not driven.

By the way, I am using Cyclone V soc, and I am using the H2F AXI bus to control the SGDMA for writing or reading data to/from DDR3. Each write and read operation transfers 8,294,400 bytes (1920x1080x2x2).

If I want to display the video using this method, how should I modify the design? Below are my project file.

Any help would be greatly appreciated.

Thanks in advance.

[ZH_Intel]

Hi there,

Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel

[ZH_Intel]

Hi there,

Good day.

We would like to suggest you to use the frame buffer instead of MGDMA.

Frame buffer is for moving video from/to DDR.

You may setup your connection as below:

Test Pattern Generator (TPG)-->Frame buffer---> CVO (Clock Video Output)-->HDMI TX.

You may refer to below document. In this document states what is the function of frame buffer, types of connection, parameter settings, application examples and more:

https://www.intel.com/content/www/us/en/docs/programmable/683416/22-1/about-the-video-and-image-processing-suite.html

Hope this answers your question.

Thank you. 

Best Regards,

ZH_Intel

[2258432]

Hello ZH_Intel,

Thanks for your assistance.

Following your instructions, I've successfully used the frame buffer, and now the video is displaying properly. Additionally, I've used memtool in Linux to check DDR3, and confirmed that the frame buffer is writing data into DDR3.

My purpose is to send this video data to a second Cyclone V SoC and display the video there. My initial plan was to use MSGDMA to transfer the video data generated by TPG to DDR3 first, and then send this data through Ethernet in Linux. The second SoC would then receive the video data and display it.

If I'm using the frame buffer, how can I send the video data out?

thanks again for your assistance.

Best regards.

[ZH_Intel]

Hi Lii Yuhang,

Good day.

May I know do you have 2 FPGA in 1 board?

It seems like you have 2 boards, is this correct?

You may setup your connection as below if you have 2 boards connected with ethernet.

Board 1: TPG-->frame buffer (write only mode) -->MSGDMA(read only)-->ethernet

Board 2: ethernet--> MSGDMA(write only to DDR3)-->frame buffer (read only mode)-->CVO-->HDMI display

Hope this answers your question.

Thank you. 

Best Regards,

ZH_Intel

[2258432]

Hello ZH_Intel,

Thanks for your guidance.

You are right, I have two Cyclone V boards.

I will first review the official documentation to learn how to use VFB's writer control and reader control, and then follow your guidance to try it out.

Thank you again, please close this thread.

Best regards.

[ZH_Intel]

Hi Lii Yuhang,

Good day.

Thank you for your reply.

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you. 

Best Regards,

ZH_Intel