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IOpll loosing stability in temperature variations

AkshayAyilliath
Beginner
617 Views

Hello

 

I'm using the iopll IP core on my Arria10 FPGA HW.
I observe that the output clock generated is getting disturbed with respect to temperature variations - to be specific, the output clock is more stable when the device is hot and highly instable when the device gets colder.
Is this a known issue on the FPGA HW or the IP core.? Is there a fix to it.?

I've attached a screenshot of the output clock probed on the oscilloscope.

But we also notice that the status of 'locked' pin of the iopll remains unchanged despite the instability at the output clock.

Please let us know your feedback for the same.
 

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4 Replies
sstrell
Honored Contributor III
586 Views

So what temperatures is this happening at?  And are you referring to the top waveform in the scope shot?  What's the bottom waveform (which looks OK)?

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AqidAyman_Intel
Employee
572 Views

Hi,


Can you specify what temperature is when the device is 'hot' and 'cold'?


Regards,

Aqid


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AkshayAyilliath
Beginner
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AqidAyman_Intel
Employee
510 Views

How the discussion going so far? Is the issue resolved?


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