JTAG FPGA Debugger_USB Blaster(UG-USB81204)

[SGADKSRI]

Hello Team,

To debug a Cyclone V FPGA, USB Blaster Debugger(UG-USB81204) is considered for debugging purpose. In JTAG interface, there are TCK, TDI & TMS are output signals and TDO input signal.

In JTAG timing specifications of debugger, following inputs are required.

1.  Please provide the TCK clock range?

2. TDI and TMS are driven by debugger from falling edge of TCK. what will be output delay of debugger while driving TDI and TMS?

3. For TDO input, what are the setup time and hold time requirement of debugger?

please provide the required inputs.

[FvM]

Hi,
there's no official specification as far as I know, but the same question has been answered in a recent thread.
Re: USB Blaster Download cable_Timing Specification - Intel Community

I you have still open points, what's the problem behind your question?

Regards
Frank

[NurAiman_M_Intel]

Hi,

Please refer to recent threads'

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/USB-Blaster-Download-cable-Timing-Specification/m-p/1644712

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any further assistance needed for this case?

Regards,

Aiman