MAX 10 Tcout value

[tulip007]

What is the spec for the Tcout value referenced in table 61 of the MAX 10 FPGA Device Datasheet? It defines it as the delay from clock pad to I/O output register but does not list specific values per device.

[ShengN_Intel]

Hi,

Check this link https://www.intel.com/content/www/us/en/docs/programmable/683794/current/i-o-timing.html for MAX 10 tco value.

This document https://www.intel.com/content/www/us/en/docs/programmable/683103/19-3/an-775-generating-initial-i-o-timing-61539.html shows how to generate initial I/O timing data for Intel FPGA devices.

Thanks,

Regards,

Sheng

[tulip007]

OK, close enough. In the second link, however, I was wondering about the following spec:

clock pad to output register delay

[ShengN_Intel]

Hi,

Clock pad to output register delay is the time it takes for a clock signal to travel from the point (at the clock pad) to the point where it triggers an action in a flip-flop or register (at the output register).

[tulip007]

Right but there is no spec for that Tcout value. Only for the Tco value. It's peculiar that the datasheet defines Tcout without also including it in table 58 of the Intel MAX 10 FPGA Device Datasheet.

[ShengN_Intel]

Hi,

In the Intel MAX 10 FPGA Device Datasheet, tco stands for tcout already. They are both the same.

Most probably clock pad to output register delay is a fixed value and had been calculated in tco so there's no necessary to state it in the datasheet anymore.

Thanks,

Regards,

Sheng