MAX V Exposed pad solder reflow problem

[Nakaj]

A reflow soldering failure occurred on the exposed pad on the bottom of the QFP64
pin device of the MAX V device. Please let me know if there is a recommended 
pattern layout for Exposed Pad.
Please let me know if there is a recommended value for the number and diameter of 
through holes to connect the exposed pad to the GND pattern.

[FvM]

Hi,
what kind of failure do you observe, missing connection or short to other pins?

I see a previous discussion related to 64-pin EQFP package https://community.intel.com/t5/Programmable-Devices/Max-V-Stencil-Design-64-Pin-Plastic-Enhanced-Quad-Flat-EQFP/m-p/1574520#M94757

I think, a comfortable option is to place vias beneath the exposed pad, this way you don't need to care for solder drain through vias. As mentioned in my previous post, EQFP package has the problem of clearance tolerance between pad and PCB, about 0.05 to 0.15 mm. You need to supply suffient solder paste to safely bridge the gap.

Regards
Frank 

[Nakaj]

Thank you for your reply.

We have an issue with exposed pad not being connected. There may not be  enough solder.

Is there reccomended pattern layout for PCB?

Regards

Nakaj

[Nakaj]

Please also tell me the recommended thickness of the solder mask.

Regards,

Nakaj

[Farabi]

Hello,

Please refer to : https://www.intel.com/content/www/us/en/support/programmable/articles/000074532.html

regards,

Farabi

[Nakaj]

Thank you for your reply.

But I would like to know about  reccomended pattern layout for PCB  and recommended thickness of the solder mask of MAX V QFP64 device.

Regards

Nakaj

[Nakaj]

Thank you for your reply.

If you find a solution please let me know.

Regards

Nakaj

[Fakhrul]

Hi Nakaj,

You can check it here: AN 353: SMT Board Assembly Process Recommendations

Hope that helps and do let me know if I can assist you further.

Regards,

Fakhrul

[Nakaj]

Thank you for your reply.

 I would like to know about  recommended thickness of the solder mask(stencil?) of MAX V QFP64 device.

About  reccomended pattern layout for PCB, I found a Cadence and mentor graphics CAD data in Intel website.

PCB design engineer tries to analyse it.

Regards

Nakaj

[FvM]

Hi,
stencil thickness is usually chosen by the assembly service provider depending on PCA technology and used pad range. As mentioned above, problem with EQFP package is the 0.05 to 0.15 mm range of exposed pad clearance. If the parts have typical 0.1 mm clearance, 120 µm standard stencil thickness should work, but for maximal 0.15 clearance you'll probably want a thicker stencil, e.g. 180 µm if it's still compatible with small pads used on the board.

I'm presuming that you have industry standard reflow profile as suggested in AN353, because another possible reason for solder failure is "cold solder joint".

Regards
Frank