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MAX10:UFM Parallel Read Timing Details

ken_51
Beginner
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Device MAX10 10M02SCE144
Environment Windows 11/Quartus Prime Lite 17.0/ModelSim ALTERA STARTER EDITION 10.5b

 

I am using Altera On-Chip Flash IP and want to read data from UFM in parallel, incrementally. The user guide for the flash memory shows a timing chart diagram for the 10M04/08/16/25/40/50. But for the 10M02, neither the diagram nor the description exist.

 

I would appreciate a detailed explanation of the lead timing for the 10M02. A timing waveform diagram would be even more helpful. Thank you in advance.

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ken_51
Beginner
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I have verified the behavior of the read from the UFM in simulation.

 

According to the timing diagram in the user guide, the readdatavalid pulse is output 5 clocks after the read pulse in the 10M04/08/16/40.

 

However, when I ran the simulation on the 10M02, to my surprise, the readdatavalid pulse came out 58 clocks after the read pulse input. This is very slow. Does it still take 58 clocks in the actual device?

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Fakhrul
Employee
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Hi ken_51,


Sorry for the delay. I'm checking this with the internal team and will get back to you with clarification.


Thanks for your patience.


Regards,

Fakhrul


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FvM
Honored Contributor II
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Hi,
I believe, you'll get a quick and reliable answer with a small test on real 10M02 device. There are obviously differerences to 10M04 and above indicated by 7.25 MHz maximal UFM clock. Unfortunately I have 10M16 as smallest type.
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Fakhrul
Employee
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Hi ken_51,

 

After re-checking the document, I realized that I may have overlooked something earlier. It is indeed expected behavior due to the significant gap between the maximum frequency for all devices in parallel mode, which is 116 MHz, and the 10M02 device, which only supports up to 7.25 MHz. This aligns with what FvM mentioned above.

 

Fakhrul_0-1721784156253.png

 

 

Regards,

Fakhrul

 

 

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ken_51
Beginner
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Thank you very much.


I already understood that the maximum clock is 7.25 MHz.

However, I did not expect that it would take more than 50 clocks to send back the readdatavalid pulse.

 

There seems to be no effective solution to this problem.

I am giving up on the 10M02 device and replacing it with a larger capacity device.

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FvM
Honored Contributor II
692 Views

Are you still checking in simulation or with real FPGA?

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ken_51
Beginner
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We gave up on 10M02 completely and replaced it with 10M08, which uses BlockRAM instead of UFM.

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Fakhrul
Employee
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Hi ken_51,


Unfortunately, we also don't have a 10M02 to test on our end. However, based on its specifications, this is expected behavior.


Regards,

Fakhrul


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Fakhrul
Employee
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