Minimum IO clock input

[Altera_Forum]

My design requires a clock input of 1MHz that can be locked with a pll. Currently i have a cyclone II fpga but in the pll megafunction i cant input a frequncy of anything lower than 50MHz or divide enough to get to 1MHz. I was wondering if what I want to do is possible? If so what device would be able to preform this?

[Altera_Forum]

IIRC, no Altera PLL will accept a clock as low a 1 MHz. 

 As for dividers, ome devices' PLLs have larger counters from others. Ie, remember that I had was unable to divide 100 MHz clock down to 1 MHz on a Cyclone II PPL but has no problems with a Cyclone III.  What I did, for the Cyclone II case, was to divide the 100 MHz clock down to 10 MHz and then divide the 10 MHz clock to 1 MHz using a clock divider implemented in logic.

[Altera_Forum]

the minimum PLL input frequency for CII should be 10 MHz, see page 66: 

 http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf