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--- Quote Start --- In the modelsim simulation, there is a signal, delay1, shows its value and undefined state(red colour) periodically. It shouldn't show unknown state based on my code. I wonder why. Pls have a look on my code attached. thanks --- Quote End --- Hi, I run your design with modelsim and I can confirm your problem. What I'm wondering about is that I could not find the signals q1 and q2 in the Waveforms. Maybe I missed something. I also setup a Quartus project and generate a netlist for simulation. With the netlist the unknow is gone. Maybe you can try it by yourself ? Kind regards GPK
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I'm not a verilog expert, but it seems that you define q1 and q2 as tables with indexes between 1 and num_shiftreg, and set delay1 with q1[no_shiftreg] or q2[no_shiftreg].
But you also initialize no_shiftreg with the value 0. So in those cases delay1 will take an uninitialized value. You should either initialize no_shiftreg with 1 or use q1[no_shiftreg+1] / q2[no_shiftreg+1]- Mark as New
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--- Quote Start --- I'm not a verilog expert, but it seems that you define q1 and q2 as tables with indexes between 1 and num_shiftreg, and set delay1 with q1[no_shiftreg] or q2[no_shiftreg]. But you also initialize no_shiftreg with the value 0. So in those cases delay1 will take an uninitialized value. You should either initialize no_shiftreg with 1 or use q1[no_shiftreg+1] / q2[no_shiftreg+1] --- Quote End --- Hi Daixiwen, you are right. q1[0] and q2[0] are never intialized, but used as input for Delay1. Kind regards GPK
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I can find the q1 and q2 under FIR(instantiation of Delay1_Redline).
If run functional simulation in qii, there is always no problem with it. thanks- Mark as New
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--- Quote Start --- I can find the q1 and q2 under FIR(instantiation of Delay1_Redline). If run functional simulation in qii, there is always no problem with it. thanks --- Quote End --- Hi, your are right , I could also find q1 and q2. The reason for your problem is here : if (count2 < 57) begin no_shiftreg <= no_shiftreg + 1; // +1 end else begin no_shiftreg <= 0; -- here you set shift_reg to "0" end if (count<count_half) begin delay1 <= q2[no_shiftreg]; -- here you set delay1 to q[0] end -- but q[0] is not defined, else -- reg [signal_mag_w-1:0] q1 [num_shiftreg:1]; begin delay1 <= q1[no_shiftreg]; end Kind regards GPK
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thanks. It solves my problem
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