On-Chip Memory Read/Write Issue

[greenlantern01]

Hello,

I am using a DE10 Standard FPGA board along with DC2390 daughter card.

I am trying to use a FIFO and On-Chip Memory (RAM or ROM) module together. Capture data from the FPGA, send that data to the FIFO, read from the FIFO and then store it in the On-Chip Memory via a DMA, and then read data from the memory from HPS. I am using the memory in dual port mode.

Could you direct me to where I can find the register map for the On-Chip Memory? I need to send chip select signals and write enable or read enable signals. 

Thank you & Regards

[ShengN_Intel]

Hi,

You may find from this link https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

Thanks,

Regards,

Sheng

[greenlantern01]

Hi Sheng,

The link that you shared only has the base address. I need to access the clken, write, writedata etc pins.

How do I access them?

Regards

[sstrell]

You don't need to access individual pins.  You use the Avalon interface of the memory for all access in Platform Designer.  The Embedded Peripherals IP user guide discusses: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/introduction.html

[ShengN_Intel]

Hi,

You may check these two links as well:

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/example-design-with-on-chip-memory.html

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/avalon-memory-mapped-interface.html

Thanks,

Regards,

Sheng

[greenlantern01]

Hi Sheng,

Thanks for sharing these links.

I am assuming the SDRAM controller is specifically made for the SDRAM. Can the DMA be used for it? Can the DMA Controller be used for the on-chip ram? 

Thanks

[ShengN_Intel]

Hi,

May I know is this another question on the DMA Controller?

Thanks,

Regards,

Sheng

[greenlantern01]

Hi Sheng,

I read the documentation for the Quartus Prime 17.0 which didn't mention DMA controller compatible with Cyclone V. I compiled the design with the Quartus version 23.1 and I see some activity on signal tap from the DMA pins. 

This is a question regarding the On-Chip Memory (RAM or ROM) Intel FPGA IP module. I have instantiated this module in the Qsys in the dual port mode and enabled "Initialize Memory Content". After loading this design on the FPGA I run a C code from the linux on the FPGA which tries to access the memory. Below is how the memory is connected to the HPS:

I am trying to mmap. What would be the base address for the on-chip memory FPGA ip? According to the HPS memory map, the ocram base address is 0xFFFF0000. I tried doing that but I get segmentation error. 

The next I tried is 0xC0000000 since it is connected to the mai axi bus, and then add the offset address which is 0x08000000 (as shown in the qsys). I am able to read a constant value from this address. Would that be correct?

How to access the second port? Do I need to mmap it again? 

[sstrell]

Check the system.h file which is created as part of the second stage bootloader based on the .sopcinfo file.  The header file includes all the macros needed for accessing components connected to the processor.

[greenlantern01]

Okay! I think I got it! Thank you!

Do I need to mmap the second port of the sram as well? I only see a single base address for the sram.

But in the qsys I see two addresses. (Shared above)

Thanks

[sstrell]

It's a true dual port RAM so the second port would get added to the header file as well.

[greenlantern01]

So I haven't built a bootloader for cyclone v.

I have used the Angstrom Linux for the DE10 Standard FPGA, programmed the fpga from the quartus software. I access the linux on the board from putty, compiled the c code and copied it to the linux and then run it from there. 

Thus I never required to follow the bootloader steps and hence I am not sure if I am looking at the right header file. Can you direct me to some documentation which shows the method for creating these header files? 

Thanks in advance and appreciate your patience!

[greenlantern01]

Update: I was able to generate header files for my project by running the below command in the NIOS II command shell:

$sopc-create-header-files <.sopc file>

Will try to use the addresses and see if it helps! 

Thanks!

[ShengN_Intel]

Hi,

Please provide us any further update or feedback whether the problem resolved with the above suggested steps?

Thanks,

Regards,

Sheng

[RichardTanSY_Intel]

May I know is there any update in regards to this case?

Do you need any further assistance?

Regards,

Richard Tan

[greenlantern01]

Hello,

I was able to make the DMA controller work. The data from the FIFO is being sent to the SRAM.

I am now trying to figure out if I can increase the DMA transfer speed. I am sweeping signals from 1Hz to 5Khz. I can see signals till 1Khz decently, however, after that the data starts breaking and is distorted after 2KHz.

Thanks for your time and assistance!

Regards