Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL Location

Altera_Forum
Honored Contributor II
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Hi! My question is, can I assign the location of a PLL in "Assignment Editor"?  

 

For example, in EP2S60, clock feeds the fapg via clk12 pin, and I want an output pin for AD clock, which needs Zero Delay Buffer feedback, and several global clocks, which need normal feedback mode. The fitter placed the former pll on pll5, I know that is OK; but another pll was placed on pll6, just on bottom of the fpga. Can I assign this pll on pll11 manually? 

 

Thank you!
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Altera_Forum
Honored Contributor II
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Hi, 

 

See thread http://www.alteraforum.com/forum/showthread.php?p=93148#post93148, complete with screenshots. 

 

Good luck, Ton
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