Problème programmation Pin

[Altera_Forum]

Hello, 

 For the passage of a signal, I use a pin in High Impedance, I declare it with :    HZ : out std_logic_vector(11 downto 0);   HZ<="ZZZZZZZZZZZZ";       My problem is with programming many CPLD EPM1270T144I5N, sometime the circuit for like the pin is in high impedance and others the pin is in a state indeterminate.   Has someone already see this probleme or know it ?     Thank you.

[Altera_Forum]

The question is unclear. What do exactly mean with "a state indeterminate". In my opinion it only exists in a simulation, flagged as 'U'. 'Z' state can only exist for an output signal, so where do you read the indeterminate state?

[Altera_Forum]

Like I have write in my message my pin is "out" then it's a output. 

 I don't read the pin but I have declare it in a 'Z' state because I have a signal routing here. I considere my pin in 'Z' state when she doesn't influence my signal.

[Altera_Forum]

Hi, 

How do you check if HZ is in high impedance ? I mean what circuit do you use to determine "high impedance" on those pins ? Indeterminated state : do you mean it is sometimes 0 and other times it is 1 ?  Many chips have a internal weak pull-up resistor on their pins.

[Altera_Forum]

Hi, 

 I have create a electronic circuit but because I haven't have much space, I pass signals under the CPLD by some pins. I declare those pins in HZ for they don't influence the signals.   My problem is sometimes the signals pass without problem and others the signals are Perturbed.

[Altera_Forum]

Hi, 

Look at http://www.alteraforum.com/forum/showpost.php?p=76202&postcount=1 I think it is similar.  I pass signals under ? the CPLD by some pins. Do you mean that HZ pins are connected to your "signals under the CPLD " ?  I declare those pins in HZ for they don't influence the signals. "don't influence" : It depends of impedance of your signal generator.  Are you sure of your connections CPLD_pin <--> "under CPLD" signals? :-)  Could you give a simple schema of your design {CPLD + extern} ?  Your english is not perfect ;-).

[Altera_Forum]

This is the part of the schéma where is the problem. 

     The connection net_31 pass on a pin of the CPLD in the routing. This pin is declared in HZ because I don't want the signal to be perturbed.

[Altera_Forum]

What do you mean by perturbated ? 

 In your schema, the net_31 will not go higher than {3.3V + VLed}.  If CPLD was not connected, your Led will emitting light if TS> {3.3V + VLed} if TS < {3.3V + VLed}, no source drives the net_31. The voltage level of net_31 would depend of Ts with R and design of the AOP (Operationnal Ampli), and it would be too sensitive.  To resume : if ts=0, net_31 is unknown.  Here, Led is functionning as a clamping Diode : is it exactly what you want ? (not sure)  Check carefully your CPLD pins option.  Try also / look at :   - unused input tri-stated pin option in Quartus (if you are using Quartus)  - inout pin  - open drain pin