Initially, I could program .sof file & run signaltap without any problem. I tried to alter the source codes like adding a new signal & output port. After that, I recompiled my design. Then, I opened the signaltap II window again & started program the .sof file. I don’t know why I cannot run the signaltap after programming the .sof file. I got the failure message “Program device to continue”…..It seems like I have missed some settings....Can anybody help on this? Thank you very much.....
A common mistake is to download a different *.sof file or a same-name file from a different directory. Another possibility is, that your hardware causes a configuration request and deletes the JTAG-loaded configuration. This can e.g. happen, if a connected AS configuration device doesn't contain a valid configuration. The on-chip configuration controller should be disabled by a Quartus programmer option in this case.
Hi FVM,Thank you for your suggestion..... The .sof file programmed into FPGA is selected from correct directory. Also,they halt on-chip configuration controller is never enabled by Quartus programmer. I also tried to enable it but I got the similar error "Program Device to continue".. Is there any other possibility reason on getting this error? Your help or anyone help would be greatly appreciated....Many thanks....
You may want to check otherwise, if the FPGA (still) holds the intended configuration image, e.g. by setting a hardware pin, toggling a LED, whatsoever. In most cases, the configuration has been deleted, e.g. because your hardware triggered NCONFIG.
Hi FvM,Thanks again for your quick response....... What I've observed is that the .sof file is programmed successfully. But I cannot run acquire data due to error "program device to continue"... One thing i forgot to mention is regarding the Logic element (LE)......90% LE is consumed in my design....Will this cause the error "program device to continue" in my signaltap II? Thanks regards, Dave
I believe the stp and design are different revision. When you start editing your design, you need to make sure in the original stp, the nodes displayed in the setup page is still valid. Because signal tap consumes LE resources, re-compiling a design may cause the stp fitting to be different from the original stp. When this happens, you'll see "Program Device to continue"To confirm this, is the stp GUI showing any nodes in red color? If it is, remove the red colored nodes and add them back. Then re-compile your design.
Hi gambit,Thanks for your response.... No,it does not show red color nodes. Anyway, I think the issue is resolved. I tried to use other FPGA family which provide higher LE. I could run signaltap successfully.