Quartus Prime Lite 23.1std crashes on elaboration of a register file

[federunco]

When synthesizing a project in Quartus with a memory element, it crashes during the MEM entity elaboration, yielding the following error:

Problem Details
Error:
Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlvalue_elab.cpp, Line: 3865
_values && pos < _values->Size()
Stack Trace:
0x118e06: vrfx_find_file(char const*, char const*, char const*) (synth_vrfx)
0x2bd6ed: VhdlCompositeValue::SetValueAt(unsigned int, VhdlValue*) + 0x53 (synth_vrfx)
0x2ef1d8: VhdlIdRef::AssignPartial(VhdlValue*, VhdlConstraint*, VhdlValue*, VhdlValue*, Net*, Array const*, unsigned int, VhdlDataFlow*) + 0x59e (synth_vrfx)
0x2e873f: VhdlIdRef::Assign(VhdlValue*, VhdlDataFlow*, Array*) + 0xfb (synth_vrfx)
0x2ead2e: VhdlIndexedName::Assign(VhdlValue*, VhdlDataFlow*, Array*) + 0xbe (synth_vrfx)
0x30eaf2: VhdlSignalAssignmentStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x1ac (synth_vrfx)
0x31573a: VhdlIfStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x5d6 (synth_vrfx)
0x31573a: VhdlIfStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x5d6 (synth_vrfx)
0x314c9d: VhdlProcessStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x1e9 (synth_vrfx)
0x2b36f2: VhdlArchitectureBody::Elaborate(VhdlBlockConfiguration*) + 0x122 (synth_vrfx)
0x2b4130: VhdlEntityDecl::CoreElaborate(VhdlSecondaryUnit*, char const*, VhdlBlockConfiguration*) + 0x44e (synth_vrfx)
0x2b9982: VhdlEntityDecl::Elaborate(char const*, Array*, Map*, VhdlBlockConfiguration*) + 0x3f2 (synth_vrfx)
0x13d179: VRFX_VERIFIC_VHDL_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0x1fb (synth_vrfx)
0x132888: VRFX_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0xc8 (synth_vrfx)
0x1b9a03: SGN_FN_LIB::elaborate(BASEX_ELAB_INFO_CORE*) const + 0x193 (synth_sgn)
0x1c34ce: SGN_FN_LIB::start_vrf_flow() const + 0xe (synth_sgn)
0x1c3cd0: SGN_FN_LIB::start(SGN_WRAPPER_INFO*) + 0x720 (synth_sgn)
0x1c843a: SGN_EXTRACTOR::single_module_extraction(HDB_INSTANCE_NAME*, HDB_ENTITY*, SGN_WRAPPER_INFO*) const + 0x10a (synth_sgn)
0x1d02be: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x14e (synth_sgn)
0x1d147f: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0x55f (synth_sgn)
0x1d047c: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x30c (synth_sgn)
0x1dc6f3: SGN_EXTRACTOR::extract() + 0x363 (synth_sgn)
0x1e8362: sgn_qic_full(CMP_FACADE*, std::vector<std::string, std::allocator<std::string> >&, std::vector<double, std::allocator<double> >&) + 0x2a2 (synth_sgn)
0x209eb: qsyn_execute_sgn(CMP_FACADE*, std::vector<std::string, std::allocator<std::string> >&, std::string const&, THR_NAMED_PIPE*, THR_NAMED_PIPE*) + 0x22b (quartus_map)
0x3b0c6: QSYN_FRAMEWORK::execute_core(THR_NAMED_PIPE*, THR_NAMED_PIPE*) + 0x296 (quartus_map)
0x3eeb2: QSYN_FRAMEWORK::execute() + 0x1b52 (quartus_map)
0x1ddd9: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x881 (comp_qexe)
0x3200e: qsyn_main(int, char const**) + 0x14e (quartus_map)
0x3e5c0: msg_main_thread(void*) + 0x10 (ccl_msg)
0x5c9c: thr_final_wrapper + 0xc (ccl_thr)
0x3e68a: msg_thread_wrapper(void* (*)(void*), void*) + 0x6e (ccl_msg)
0xc096: mem_thread_wrapper(void* (*)(void*), void*) + 0x96 (ccl_mem)
0x91a8: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x5cdf: thr_thread_wrapper + 0x15 (ccl_thr)
0x4058a: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa8 (ccl_msg)

0x29e40: __libc_start_main + 0x80 (c.so.6)
0x1b649: _start + 0x29 (quartus_map)

End-trace

Executable: quartus
Comment:
None

System Information
Platform: linux64
OS name: Ubuntu 22.04.4
OS version: 22

Quartus Prime Information
Address bits: 64
Version: 23.1std.0
Build: 991
Edition: Lite Edition

mem.vhd file:

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;

ENTITY MEM IS
GENERIC(
 word_size: integer := 8; 
 addr_size: integer := 10
);
PORT (
 CLK, RST, CS, WR, RD: IN std_logic;
 DATA_IN: IN std_logic_vector(word_size-1 DOWNTO 0);
 ADDR: IN std_logic_vector(addr_size-1 DOWNTO 0);
 DATA_OUT: OUT std_logic_vector(word_size-1 DOWNTO 0)
 );
END MEM;

ARCHITECTURE behavioral OF MEM is
TYPE reg_type IS ARRAY (0 to 1023) OF std_logic_vector(word_size-1 DOWNTO 0);
SIGNAL reg_file: reg_type;
BEGIN
PROCESS(CLK, CS, RD, ADDR, reg_file)
BEGIN
IF (rising_edge(CLK)) THEN
IF (RST = '0') THEN
 reg_file(0 to (2**addr_size)-1) <= (others => (others => '0'));
ELSIF (CS = '1' AND WR = '1') THEN
 reg_file(to_integer(unsigned(ADDR))) <= DATA_IN;
END IF;
END IF;
IF (CS = '1' AND RD = '1') THEN
 DATA_OUT <= reg_file(to_integer(unsigned(ADDR)));
ELSE
 DATA_OUT <= (others => 'Z');
END IF;
END PROCESS;
END behavioral;

[RichardTanSY_Intel]

The problematic code seems to come from this line:

reg_file(to_integer(unsigned(ADDR))) <= DATA_IN;

This is due to the old code running in Quartus synthesis tool and there is no plan to fix/change it.

Try to change the code construct to below code and it will pass the synthesis:

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;

ENTITY MEM IS
GENERIC(
 word_size: integer := 8; 
 addr_size: integer := 10
);

PORT (
 CLK, RST, CS, WR, RD: IN std_logic;
 DATA_IN: IN std_logic_vector(word_size-1 DOWNTO 0);
 ADDR: IN std_logic_vector(addr_size-1 DOWNTO 0);
 DATA_OUT: OUT std_logic_vector(word_size-1 DOWNTO 0)
 );
END MEM;

ARCHITECTURE behavioral OF MEM is
TYPE reg_type IS ARRAY (0 to 1023) OF std_logic_vector(word_size-1 DOWNTO 0);
SIGNAL reg_file: reg_type;
BEGIN
PROCESS(CLK, CS, RD, ADDR, reg_file)
BEGIN
IF (rising_edge(CLK)) THEN
IF (RST = '0') THEN
 reg_file(0 to (2**addr_size)-1) <= (others => (others => '0'));

ELSIF (CS = '1' AND WR = '1') THEN
 -- Original code
 -- reg_file(to_integer(unsigned(ADDR))) <= DATA_IN;
-- Alternative
 for i in 0 to (2**addr_size)-1 loop
   if to_integer(unsigned(ADDR)) = i then
       reg_file(i) <= DATA_IN;
   else
       reg_file(i) <= reg_file(i); -- Redundant assignment to maintain synthesizability
   end if;
 end loop;

END IF;
END IF;

IF (CS = '1' AND RD = '1') THEN
 DATA_OUT <= reg_file(to_integer(unsigned(ADDR)));

ELSE
 DATA_OUT <= (others => 'Z');

END IF;
END PROCESS;
END behavioral;

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know. 

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Best Regards,

Richard Tan

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