Quartus v14.0 Altera_PLL IP targeting Cyclone V (5CEFA7) does not lock

[Altera_Forum]

board -  

Has a 5CEFA7F23I7 (Cyclone V E A7). The analog PLL power supply pins (6 VCCA_FPLL pins) have a common 2.5V rail, decoupled with approx. 64uF, split across 16 or so caps. The 2.5V is driven by an LDO regulator with a 5V input.  A 48MHz 3.3V 50ppm XO oscillator is used as the only clock to the FPGA - it drives FPGA pin CLK2P.  fpga -  The ALTERA_PLL megawizard is used to generate the v14.0 PLL IP core. I used the following parameters: PLL Mode = Integer-N RefClk Freq = 48.0 MHz Operation Mode = normal Feedback clock = Global Clock Locked output port enabled No switchover, no cascading, no DPS  PLL Auto Reset enabled  PLL Bandwidth Physical Output params enabled:  M = 16 N = 2 Divide-Factor (C-counter) = 2 Resulting output clock frequency = 192.0 MHz The advanced parameters tab indicates a PLL output VCO frequency of 384.0MHz that will be divided down by 2 to my desired 192.0MHz clock.   This results in a core module with 4 I/O: refclk - my global input 48.0MHz clock rst - hard-coded to '0' right now outclk_0 - my desired 192.0MHz clock locked - pll_locked, going to a board LED I am also driving a simple counter off the 192.0MHz clk that will toggle an LED at 250ms.   problem -  My problem is the PLL never achieves lock (PLL LED never lit), and I never see the PLL output clock toggle (Clock toggle LED never lit).  Here is a paste from my Fitter PLL Usage Summary Report:  TEST:TEST_config|adc_ctrl_pll:adc_pll|adc_ctrl_pll_0002:adc_ctrl_pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL  -- PLL Type Integer PLL  -- PLL Location FRACTIONALPLL_X89_Y1_N0  -- PLL Feedback clock type Global Clock  -- PLL Bandwidth Auto (Low)  -- PLL Bandwidth Range 1200000 to 600000 Hz  -- Reference Clock Frequency 48.0 MHz  -- Reference Clock Sourced by Dedicated Pin  -- PLL VCO Frequency 384.0 MHz  -- PLL Operation Mode Normal  -- PLL Freq Min Lock 37.500000 MHz  -- PLL Freq Max Lock 87.500000 MHz  -- PLL Enable On  -- PLL Fractional Division N/A  -- M Counter 16  -- N Counter 2  -- PLL Refclk Select  -- PLL Refclk Select Location PLLREFCLKSELECT_X89_Y7_N0  -- PLL Reference Clock Input 0 source clk_0  -- PLL Reference Clock Input 1 source ref_clk1  -- ADJPLLIN source N/A  -- CORECLKIN source N/A  -- IQTXRXCLKIN source N/A  -- PLLIQCLKIN source N/A  -- RXIQCLKIN source N/A  -- CLKIN(0) source clock~input  -- CLKIN(1) source N/A  -- CLKIN(2) source N/A  -- CLKIN(3) source N/A  -- PLL Output Counter  -- TEST:TEST_config|adc_ctrl_pll:adc_pll|adc_ctrl_pll_0002:adc_ctrl_pll_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  -- Output Clock Frequency 192.0 MHz  -- Output Clock Location PLLOUTPUTCOUNTER_X89_Y2_N1  -- C Counter Odd Divider Even Duty Enable Off  -- Duty Cycle 50.0000  -- Phase Shift 0.000000 degrees  -- C Counter 2  -- C Counter PH Mux PRST 0  -- C Counter PRST 1

[Altera_Forum]

is this a custom board? 

did you checked the reference resistor for pll? from pin connection guideline:  Reference Pins RREF_TL - Input Reference resistor for transceiver and PLL: If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

[Altera_Forum]

--- Quote Start ---  approx. 64uF, split across 16 or so caps.  --- Quote End ---   Approx. 4uF per cap - what are these caps? Do you have any low value, low ESR ceramic caps as well? Cyclone V devices, particularly the PLL rails, won't tolerate much noise. A LDO will help but only if it has sufficient decoupling close to the appropriate FPGA power pins.  Have you tried any other PLL configurations? Reduce the multiplier.  Finally, in line with comments from lars, have you followed all the Cyclone V connection guidelines? See  cyclone® v device family pin connection guidelines (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/pcg-01014.pdf). An incorrect or missing RREF_TL resistor is a very likely candidate.  Cheers, Alex