Serial Flash Controller II Intel FPGA IP and Nios II connection

[HAlex]

Hello

I am using EP4CGX150CF23C8 connected to EPCQ128ASI16N flash at ASx1 mode.

Connection designed by Platform designer at following mode:

Clock in that used by CPU (Nios II processor) is 100Mhz.

As maximum frequency to Serial Flash Controller is 50Mhz - the clock to the Flash controller connected from the PLL's output (50Mhz).

Data and instructions busses of the Serial Flash Controller connected to the Nios through 100Mhz Avalon busses directly without any crossing bridge.

After project compilation I get warning 15064:

This warning related to ALTERA_DCLK_OBUF (DCLK of serial flash) feeds by 50Mhz from PLL.

No action related to PLL help to get rid of this warning (changing PLL's, PLL's output).

The only thing that helps is to define Clock Source as 50Mhz and connect it both to the Nios and to the flash.

But I want to run Nios at 100Mhz so it is not a solution for me.

I have 2 questions:

1. Is it ok to connect Serial Flash Controller II Intel FPGA IP as I did - directly to the Avalon busses without crossing bridge and to connect clock to the PLL's output? Or I can encounter a clock domain issues?

2. What should be done to get rid of the warning 15064? Or I can simply ignore it?

Thank you

Alex

Thank you

Alex  

[hareesh]

Hi HAlex,

The GSFI (Generic Serial Flash Interface) Intel® FPGA IP provides access to Serial Peripheral Interface (SPI) flash devices. To control EPCQ128ASI16N flash device you can use GSFI IP. GSFI is available in Quartus pro version only. In Quartus standard use the Altera Generic Quad SPI Controller 2.

GSFI Documentation :

https://www.intel.com/content/www/us/en/docs/programmable/683419/22-2-20-2-1/user-guide.html

thanks,

[HAlex]

Hello

I have Quartus Prime Standard edition 21.1. also my FPGA is Cyclone IV (EP4CGX150CF23C8).

Regarding the Altera Generic Quad SPI Controller 2 look at page 262:

Even EPCQA device (EPCQ128ASI16N) is not mentioned still probably this core need a quad mode of AS.

Also in Platform designer this core is greyed (when 'Show IP for all device families' is marked):

And it simply disappeared when marked 'Show IP for active device family'.

As I understand Cyclone IV is not supporting ASx4 mode.

Thank you

Alex 

[hareesh]

Hi @HAlex ,

Generic Serial Flash Interface IP is supported to Cyclone IV. you can find Generic Serial Flash Interface IP user guide in bellow link.

https://www.intel.com/content/www/us/en/docs/programmable/683419/21-2-20-1-1/device-family-support.html 

thanks,

[HAlex]

Hello

I wrote above that I have a Quartus Prime Standard edition.

Generic Serial Flash Interface is supported only at Pro edition.

Look your posts above and in the following link:

https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/HAL-API-for-the-Generic-Serial-Flash-Interface-FPGA-IP-altera/td-p/1391666/page/2

Thank you

Alex

[hareesh]

Hi

that is correct, that is why in the cyclone v example they use IOWR & IORD. that example link sharing here. once try this one.

link:

https://www.intel.com/content/www/us/en/design-example/714711/cyclone-v-generic-serial-flash-interface-intel-fpga-ip-core-reference-design.html 

Thank you,

[HAlex]

Hello

This example specified for Cypress and Micron flashes and not uses HAL API functions.

So you mean that I can't use Serial Flash Controller II Intel FPGA IP that I defined connected to Intel's flash EPCQ128ASI16N and use HAL API functions and make things in an easier way?

Thank you

Alex

[hareesh]

Hi @HAlex ,

If you want to use the Serial Flash Controller II Intel FPGA IP, you need to change the NIOS frequency to 50 MHz. Then you can use that IP because we don't have any bridge IP to synchronize both of them. Through PLL, we can synchronize CLK only. Data line we can't, so we will lose some data if you do that.

If you don't want to change the NIOS frequency, the GSFI IP is the only option, and we don't have HAL drivers in Quartus Prime Standard Edition. Then follow the shared example format only because I shared that example.

thanks,

[HAlex]

Hello

I will try to work with GSFI core according the example you mentioned without HAL API and with IOWR and IORD commands.

You wrote that there is no bridge IP to synchronize between 100Mhz Nios and slower components.

In my project I am using AVALON-MM Clock Crossing Bridge for connection to Remote Update INTEL FPGA IP (that need to work with maximum clock of 20Mhz). The clock of 20Mhz is produced from PLL.

The connection is as below:

My questions:

1. Is it a correct way of connection for Remote Update IP?

2. I connected also components like RS232 UART and PIO's IP's (with input clock of 50Mhz) through AVALON-MM Clock Crossing Bridge. You think it is not necessary and I can connect them directly to 100Mhz Avalon bus and Nios?

3. You think it is impossible to use  AVALON-MM Clock Crossing Bridge for connection to Serial Flash Controller II Intel FPGA IP?

Currently my hardware board with FPGA is still at production so all these questions are theoretical as I can't test it with a real hardware.

Thank you

Alex

[hareesh]

Hi @HAlex,

the problem of adding a bridge between a Nios and a flash is that Nios will not know that there is a flash behind the bridge. it only sees a bridge. the other problem is running 2 devices with different clocks. you have to be careful so they can communicate correctly. there is a parameter (isthisamemory) in the sopcinfo that you can manually change so the Nios sees a memory behind a bridge.

RS232 UART and PIO's IP's can support 100MHz clk. i think AVALON-MM Clock Crossing Bridge not required in between of them.

Thanks,

[HAlex]

Hello hareesh

You think that the Remote update IP is connected correctly through AVALON-MM Clock Crossing Bridge?

All other components (GSFI, PIO & UART) are now used and connected as you suggested.

Thank you

Alex

[hareesh]

Hi @HAlex,

pls go through the bellow given example of remote update IP

link:

https://www.intel.com/content/www/us/en/design-example/714988/cyclone-v-remote-system-upgrade-over-uart-based-on-nios-ii-processor-with-epcq.html? 

Thanks,

[HAlex]

Hello

At this example Remote Update IP and EPCQ (Serial flash) controller IP - both running on 20Mhz connected directly to the 

Avalon bus and Nios running on 50Mhz without any bridge !!!!

According all written at this post above it is not an optimized connection?

What you say about it?

Thank you 

Alex

[hareesh]

Hi @HAlex,

sorry for delay. for your design conformation i have taken little bit time.

connections of remote update IP and AVALON-MM Clock Crossing Bridge in your design are correct. no need to change and don't forgot setting PLL output to 20MHz.

I think you got solution for your issues. if you don't have any another quires i'll close the case. Can you confirm?

Thanks,

[HAlex]

Hello hareesh

First of all I have the same opinion like your's that it is problematic to connect components with different clock source to the same bus.

But I just encountered 3 sources with a different attitude.

1. Your last example. Nios do run on 50Mhz, while Remote Update IP and EPCQ (Serial flash) controller IP - both running on 20Mhz. Look below: definition of PLL and connection of Nios (to outclk1 - 50Mhz), Remote update and Serial flash controller (outclk0 - 20Mhz).

2. Look also at the following link posted in the community:

https://community.intel.com/t5/FPGA-Intellectual-Property/Serial-Flash-Controller-IP-Clock-Speed/m-p/654287#M18267

3. Intel's FSE told me few weeks ago by phone to connect Nios (with 100Mhz) and Serial Flash Controller II Intel FPGA IP (who can get maximum 50Mhz) directly to the same Avalon bus and it "will be ok".

I just want to clarify this issue even for other user's (personally now I am implemented it with GSFI IP running on 100Mhz and connected Remote update IP through AVALON-MM Clock Crossing Bridge as you suggested).

If needed INTEL should modify and fix provided documentation and examples.

Thank you

Alex

[hareesh]

Hi

I can understand your problem. from my side I'll rise the ticket about this issue.

Thank you.