Serial data from shift register to FIFO

[Altera_Forum]

Hi, 

let's assume conditions:  Receive domain: Data clock : 125 MHz Data encoded with with 5b/4b method Data frame contains 32 * 64 bits (4bits before encoding - 40 * 64 bits in 5bit version) Frame frequency is 44 kHz  The begin of the frame is synchronized with following bits "11000"  So first i have to detect the beginning of the frame - i use for this 15 bit shift register. Serial data goes into the shift registers , and sync is asserted when the most significant 10 bits are 1100011000 and the least significant are different from 11000. Shift register is clocked with 125 MHz.  My object is to: After getting sync flag, i need to decode 5 lsb bits of shift register into 4 bits. And put them into the FIFO.   After decoding data from 5 bit to 4 bit i get 25 MHz clock to drive the wrclk of the fifo.  So my question is ->  How to correclty get this 5 bits (then 4 bits) into the fifo ?  I assume that this 25 MHz clock is derived directly from this 125 MHz clock , so the are synchronized. I should also assert correctly wrreq signal in fifo - and use a counter to write only these 32 * 64 bits and nothing else.   wrreq must be asserted somehow before the rising edge of wrclk (falling edge) ? What if i assert it in the rising edge? Will data be put into the fifo, or on the next cycle? Or something wrong will happen ?  I suppose that i should use a synchronizer for the sync flag in 125 Mhz- but don't know how to do it - it will give some delay to the sync in 25 MHz domain. I will lose then the actual data from the shift register (it will be shifted with 125Mhz clocks before i will be able to correctly read those 5 bits and put them into 25 Mhz clock domain) ?  Sorry for the mess, thanks for any suggestions and help best regards madness

[Altera_Forum]

Hi madness, 

 Ignore the FIFO to start with.  Create a design clocked at 125MHz, which contains the shift-register, your synchronization logic, and a counter. Use the counter to generate the output data valid/enable pulse at the 25MHz output data rate, i.e., every 5th input bit period.  Once you get that working, writing to a FIFO is simple, you connect the enable bit to the write-enable on the FIFO. If you wanted to use a dual-clocked FIFO, you could use the 125MHz as the reference to a PLL and have that PLL generate a 25MHz clock. That 25MHz clock could then be used on the other port of the FIFO. However, you could probably also leave your design running at 125MHz and simply use the data valid indicator along with the data.  Create a Modelsim simulation of this design, and feed it a known serial bit stream and confirm that it decodes correctly.  Cheers, Dave

[Altera_Forum]

Hi Dave,  

thanks for the reply, sure you're right i should do this step by step.  Here is what i came up with as soon as i read your post:   LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY receiver IS PORT( clk_125_in : in std_logic; data_in : in std_logic; wrclk_fifo : out std_logic; -- wrclk to fifo wrreq_out : out std_logic; -- drivers wrreq of fifo data_out : out std_logic_vector(3 downto 0) -- data from the decoder - latched with 25 mhz derived clock ); END receiver; ARCHITECTURE arch OF receiver IS signal synchronized : std_logic; signal shift_register : std_logic_vector(14 DOWNTO 0); signal clk_divider: integer range 0 to 5; signal clk_25_derived : std_logic := '0'; -- is it needed for synthesis ? and clock dividing ? -- is it initialized somehow quartus synthesis tool signal fifo_wrreq : std_logic; signal data_decoded_to_fifo : std_logic_vector(3 downto 0); signal data_counter : integer range 0 to 511; -- data_counter needs to count to 64*32/4 = 512 and then deassert wrreq BEGIN shift_register_process : process (clk_125_in) begin if clk_125_in'event and clk_125_in = '1' then shift_register <= shift_register(14 downto 1) & data_in; end if; end process shift_register_process; sync_detect : process (clk_125_in, shift_register) begin if clk_125_in'event and clk_125_in = '1' then if ((shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN synchronized <= '1'; else synchronized <= '0'; end if; end if; end process sync_detect; clk_125_div_process : process (clk_125_in) begin if clk_125_in'event and clk_125_in = '1' then if (clk_divider=4) then -- not sure here right now if it should be 4 or 5 -- to get 5 clock division clk_25_derived <= NOT clk_25_derived; clk_divider <= 0; else clk_divider <= clk_divider + 1; end if; end if; end process clk_125_div_process; fifo_wrreq_gen : process (clk_25_derived) begin if clk_25_derived'event and clk_25_derived = '1' then if synchronized = '1' then fifo_wrreq <= '1'; data_counter <= 0; elsif data_counter = 511 then fifo_wrreq <= '0'; else data_counter <= data_counter + 1; end if; end if; end process fifo_wrreq_gen; wrreq_out <= fifo_wrreq; data_out <= data_decoded_to_fifo; -- i can simply put it directly from process -- data_decoder into the output? wrclk_fifo <=clk_25_derived; data_decoder : process (clk_25_derived) begin if clk_25_derived'event and clk_25_derived = '1' then case shift_register(4 downto 0) is when "11110" => data_decoded_to_fifo <= "0000"; when "01001" => data_decoded_to_fifo <= "0001"; when "10100" => data_decoded_to_fifo <= "0010"; when "10101" => data_decoded_to_fifo <= "0011"; when "01010" => data_decoded_to_fifo <= "0100"; when "01011" => data_decoded_to_fifo <= "0101"; when "01110" => data_decoded_to_fifo <= "0110"; when "01111" => data_decoded_to_fifo <= "0111"; when "10010" => data_decoded_to_fifo <= "1000"; when "10011" => data_decoded_to_fifo <= "1001"; when "10110" => data_decoded_to_fifo <= "1010"; when "10111" => data_decoded_to_fifo <= "1011"; when "11010" => data_decoded_to_fifo <= "1100"; when "11011" => data_decoded_to_fifo <= "1101"; when "11100" => data_decoded_to_fifo <= "1110"; when "11101" => data_decoded_to_fifo <= "1111"; when others => null; end case; end if; end process data_decoder; end; i have become familiar with VHDL code sytnax - but i still don't "feel" everything  I will test this tommorow - going to sleep right now :)  please just take a look on the design - any suggestions ?  i assumed that wrreq will be enabled at the beggining of the frame, and deasserted and the end (after counting 32*64/4 - 4 because of decoded nibble that goes to fifo)  wrclk is derived from the 125 clock.  Will there be any problems with such clock ? i need to use this that way bacause the data will be as farest i know recovered form fiber optic cable - data and clock will be RECOVERED - i know that this topic is not easy - perhaps this recovered clock from serial data won't be perfect - but i suppose if i want to use a 25 Mhz clock as wrclk of fifo it should be derived from this clock.  will i be able to latch a data into the fifo using this method?  any other considerations?  thanks  madness

[Altera_Forum]

--- Quote Start ---   i have become familiar with VHDL code sytnax - but i still don't "feel" everything   --- Quote End ---    You will get a clearer understanding when you simulate that code using Modelsim, since you will be able to see all of the internal signals.    --- Quote Start ---   please just take a look on the design - any suggestions ?   --- Quote End ---   Simulate it.   The first thing you will find is that you will have lots of undefined signals. I'd recommend adding a reset to the top-level entity and adding reset to each of the synchronous processes.    --- Quote Start ---   i assumed that wrreq will be enabled at the beggining of the frame, and deasserted and the end (after counting 32*64/4 - 4 because of decoded nibble that goes to fifo)   --- Quote End ---     The FIFO write-request should only pulse every 5th clock, during the same clock phase as the data is valid. You'll want to look at the simulation to get the timing right.    --- Quote Start ---   wrclk is derived from the 125 clock.   --- Quote End ---    No. wrclk should be 125MHz. There is no need to have two clocks in this component. This component operates at 125MHz, but generates valid output data at 1/5th that rate, as indicated by the wrreq pulses on the output.  Have you used Modelsim before? If not, look at this simple example:  http://www.alteraforum.com/forum/showthread.php?t=32386  Cheers, Dave

[Altera_Forum]

Hi, thanks Dave for help, 

i will do as you suggested, i have just started working with the project - also found out how to read bits from a text file, write a testbench and use modelsim itself to do the simulation.  Couple of questions for right now:  1) i won't have a reset button or stuff like that, i will use pll fed by 125 mhz clock to generate 375 mhz (for data and clock recovery from optic fiber) - and 125 Mhz to read from the FIFO.  Can i use a pll locked signal to do the reset ? if locked = 0 than reset all signals?   2) why should i reset all signals ? are there any exeptions ? the synthesis tool won't do it for me in the device after fitting ?  3) I want to put those 5 bits into the FIFO, and with rdclk (maybe this 125mhz) to read 40 bits - and to some operations on them like 5b/4b decoding and sending forward etc.  Reading 40 bits will give me time to do some manipulation on the data.  Should i have any problems with reading those 40 bits ? That's a lot of bits to be read from FIFO at once ?  4) Thanks for the idea of using this 125 mhz clock as wrclk - one question here, should i put this clock as   wrclk <= not 125mhz_recovered;So wrreq is asserted with not inverted clock and is '1' when rising_edge of wrclk.  I suppose i can't in the same clock cycle of 125Mhz clock to assert wrreq and have the rising edge of that clock in wrclk pin ? Data will be correctly put then into the fifo ?  So should i use inverted or not ?  best regards  madness

[Altera_Forum]

--- Quote Start ---   Couple of questions for right now:  1) i won't have a reset button or stuff like that, i will use pll fed by 125 mhz clock to generate 375 mhz (for data and clock recovery from optic fiber) - and 125 Mhz to read from the FIFO.  Can i use a pll locked signal to do the reset ? if locked = 0 than reset all signals?    --- Quote End ---    Yes, you can use the pll_locked output as a reset to your logic.  If you have a part of the design that does not have a reset signal, then you can initialize the signal, eg.,  signal never_reset : std_logic_vector(3 downto 0) := (others => '0');  and the simulator will then start with this signal as all zeros, rather than unknown.    --- Quote Start ---   2) why should i reset all signals ? are there any exeptions ? the synthesis tool won't do it for me in the device after fitting ?   --- Quote End ---    The FPGA will have a defined state for the registers after configuration. The statement above will set that power-on value (assuming the device supports the power-on setting you specify).  Resets are very useful for reinitializing the system, without having to reconfigure the FPGA.  You don't always have access to a reset signal. Eg., if you create JTAG logic, there is no reset signal from the Altera JTAG IP core, so you have to use the initialization as I show above.    --- Quote Start ---    3) I want to put those 5 bits into the FIFO, and with rdclk (maybe this 125mhz) to read 40 bits - and to some operations on them like 5b/4b decoding and sending forward etc.  Reading 40 bits will give me time to do some manipulation on the data.  Should i have any problems with reading those 40 bits ? That's a lot of bits to be read from FIFO at once ?   --- Quote End ---     No need for a FIFO for this, just use a shift-register.    --- Quote Start ---    4) Thanks for the idea of using this 125 mhz clock as wrclk - one question here, should i put this clock as   wrclk <= not 125mhz_recovered;So wrreq is asserted with not inverted clock and is '1' when rising_edge of wrclk.   --- Quote End ---     No, there is no need. The 125MHz clock should be routed to all components that operate at 125MHz. Timing constraints would then be applied to the design, and the synthesis tool will indicate whether the design meets timing. 125MHz should be fine in most newer generation devices, eg., Cyclone IV.  Cheers, Dave

[Altera_Forum]

thanks again :) 

 1) So the  signal never_reset : std_logic_vector(3 downto 0) := (others => '0'); is rather for simulation ? so i wouldn't have 'U' value and problems with never_rest <= not never_reset; in simulation ?  2) i suppose that normal value for flip-flops would be '0' at q ? if i have this power-on reset option (like in cyclone III) then i cant make the default value of q to '1' ?  3) Clock of the shift register would be recovrered from data - with this clock i should load these 40 bits to registers, clocked by 125 mhz clock . So there should be some synchronization steps?  The whole idea is that i want to use a 'normal' clock in all data manipulation, than using this recovred - i don't think that this would be a good idea to use this recovred clock in whole device - it's just a feeling :)  best regards

[Altera_Forum]

--- Quote Start ---   1) So the  signal never_reset : std_logic_vector(3 downto 0) := (others => '0'); is rather for simulation ? so i wouldn't have 'U' value and problems with never_rest <= not never_reset; in simulation ?   --- Quote End ---  Its used in both simulation and synthesis.    --- Quote Start ---   2) i suppose that normal value for flip-flops would be '0' at q ? if i have this power-on reset option (like in cyclone III) then i cant make the default value of q to '1' ?   --- Quote End ---  Try it and see. Each device has its own synthesis restriction. In some cases, if you ask for a reset value of 1 and the device cannot support it, it will reset the register to 0, and then use a not gate to turn it into a 1.    --- Quote Start ---   3) Clock of the shift register would be recovrered from data - with this clock i should load these 40 bits to registers, clocked by 125 mhz clock . So there should be some synchronization steps?   --- Quote End ---  Clock recovery is independent of this particular block of code. Get this code working before you think about that.  How were you thinking of implementing clock recovery from your data? I don't think there is a hard-IP for clock recovery at 125MHz.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  How were you thinking of implementing clock recovery from your data? I don't think there is a hard-IP for clock recovery at 125MHz.   --- Quote End ---    A friend of mine did 2 different circuits for that. I have a 125 MHz crystal on pcb, and one circuit works at 375 MHz (after multiplying 125mhz in pll block) on cyclone III and it worked, also 500 Mhz - it also worked - but it's over datasheet capabilities of cyclone III family ;)  so i assume that it will work, and i need to get the data and do some manipulation on it, and then send it in the same manner with frame synchronization.  The write to the FIFO would be essantialy done with 25 MHz (5 bits in - 125 Mhz / 5), and read out 40 bits with 25 Mhz clock from PLL (divied) to give me some time to do some stuff (5b/4b decoding as i mentioned earlier and also addng bits from different source to this frame in a specified position).   Or even to read those 40 bits with 125 Mhz clock from PLL (no multiplication) - this would give me even more time if i needed it  I thought that using FIFO would be a good solution.  Cheers, thanks for your patience Dave :)

[Altera_Forum]

--- Quote Start ---  A friend of mine did 2 different circuits for that. I have a 125 MHz crystal on pcb, and one circuit works at 375 MHz (after multiplying 125mhz in pll block) on cyclone III and it worked, also 500 Mhz - it also worked - but it's over datasheet capabilities of cyclone III family ;)   --- Quote End ---    Does this circuit implement phase-shifting of the PLL to track the input data stream?  When you have a continuous bit stream clocked by a nominal 125MHz source on another board, your local logic needs to track the frequency of that bit stream. The local 125MHz and remote 125MHz will generally not be identical.  You could use the local PLL and increase the sampling frequency by say 8x so that you sample the incoming bit stream at 1Gbps. You would then need some logic to decide where the 'center' of the data eye pattern is (to the nearest 1ns). The location of 'center' would be adjusted every now and then by inserting or dropping a 1ns sample.  The output of this clock-and-data recovery logic would be a 125MHz bit-stream. This bit-stream is 4/5b encoded, so you would then decode it, and convert it to parallel words.  The bit stream recovery and decoding to parallel words are two separate functional blocks. Code them that way, as they'll be easier to debug.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Does this circuit implement phase-shifting of the PLL to track the input data stream?  --- Quote End ---  I don't know the details right now.    --- Quote Start ---  You could use the local PLL and increase the sampling frequency by say 8x so that you sample the incoming bit stream at 1Gbps  --- Quote End ---  Won't there be any problems with that big clock ? I'm working on Cyclone III device - it's max clock from the datasheet is as farest i remeber smth about 470 Mhz clock - when useing 500 MHz - Quartus gives some warnings.  What about power consideration (silicon overheating) and EMI?   I have just started working on getting those 5 bits to FIFO.  I Wrote the testbench for clock generation and to read bitstream from a file. Every falling edge of the clock in testbench i update serial input data pin, so in my entity i latch the correct bit with rising_edge  BTW - should i use event and clock = '1' or rising_edge(clock) ?  here is the function for setting synchronization flag:   process (clk_125_in, shift_register) variable sync_var : std_logic; begin if clk_125_in'event and clk_125_in = '1' then if (( shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN sync_var := '1'; else sync_var := '0'; end if; synchronized <= sync_var; end if; end process i tried using only a signal instead of sync_var - same result, and then used variable - cause thought that it was smth with updating the signal in a process ;o i also and i suppose it doesnt really matter put  synchronized <= sync_var;  after last end if;  the problem is that flag is asserted one clock cycle after correct condition. So i wrote also smth like that to see this 5 bits (of course they are also seen in the waveform):  process (synchronized) is begin if synchronized = '1' then data_out <= nrzi_in_shift_register(4 downto 0); else data_out <= "00000"; end if; end process;  to illustrate this here is result from my testbench:  https://sites.google.com/site/pauldab/home/wave.jpg   sync flag should be set in the Cursor 1 time/edge instead of it is asserted after 1 clock of 125 clock cycle.  Then 5 bits are wrong - i lost 1 bit , and i will not get valid data every 5th clock enable.  What i did wrong?:)   best regards

[Altera_Forum]

--- Quote Start ---   Won't there be any problems with that big clock?   --- Quote End ---  Yes. You will be limited to whatever frequency your device can sample at.  Depending on the speed grade, some of the Cyclone devices can sample up to 800Mbps (400MHz DDR).    --- Quote Start ---   What about power consideration (silicon overheating) and EMI?    --- Quote End ---  You should always perform a power analysis.    --- Quote Start ---   I have just started working on getting those 5 bits to FIFO.   --- Quote End ---  Good. Solve one problem at a time.    --- Quote Start ---   I Wrote the testbench for clock generation and to read bitstream from a file. Every falling edge of the clock in testbench i update serial input data pin, so in my entity i latch the correct bit with rising_edge   --- Quote End ---  There's no need to use two clock edges. Try to always use the rising edge.  To make the simulation look a little more realistic, do something like this:   architecture of ... -- Nominal clock-to-output delay constant tCO : time := 1 ns; begin ... x <= <value from file> after tCO; ... This makes the signals appear 1 ns after the clock edge.  When you look at that signal in the simulation, its obvious that its the next rising edge that registers the signal in the next register.    --- Quote Start ---   BTW - should i use event and clock = '1' or rising_edge(clock) ?   --- Quote End ---  Use rising_edge(clock). If you look for the definition in the library, you'll see it is (clock'event and clock = '1').    --- Quote Start ---   the problem is that flag is asserted one clock cycle after correct condition.    --- Quote End ---  If you want a pulse when the condition is met, then you need to use combinatorial logic, i.e.,   process (shift_register) begin if ((shift_register(14 downto 5) = "1100010001") and (shift_register( 4 downto 0) /= "11000")) THEN synchronized <= '1'; else synchronized <= '0'; end if; end process In this case, do not put after tco after the synchronized signal, since its not a register output. You could create a tD for a combinatorial delay and use that, but generally its not that useful to add extra delay to combinatorial signals in the simulator.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

thanks to your help i finally finished the fifo receiver part :) here is the result:   https://sites.google.com/site/pauldab/home/wave2.jpg    You can see here 2 frames - one full and only the beginning of the second.  There are 2 pulses detecting the beginning of frames. And below that are wrreq pulses every 5th bit (i'm also doing here asynchonous 5b/4b decoding)  i put the 4 bit wide data signal, and the lowest 5 bits of my receiving shift register - just to compare if decoding is correct.  I have prepared txt file with those frames, chosen arbitrary 32 bit with decimal valuses of  "1110000222" and "4210000001", encoded them into 5bit and put the mix of those into txt to create after sync bits 64 channels of data.  I thought that my fifo is written only if the sync is detected and writes after that 64 channels - so i decided there won't be any wrempty/wrfull flags. Just rdusedw. I will use a state machine to read the data from fifo if there are 32 bits in the fifo (8 words - reading if there are available 32 bits will also give me the ability to empty the fifo), and to other manipulations.   For now i used a 125 Mhz clock for the state machine, the rdusedw increments by one in 320 ns, so dividing it by 125 clock period gives me 40 clock cycles to do some stuff : ) (8 times more bits read at once , and 5 times faster rdclk = 5*8 = 40 - that's correct with theory :) )  For now i haven't done the other logic, so state machine simply asserts rdreq and reads the data if fifo is half full (msb of rdusedw).  And at q_fifo i get for "1110000222" result of "3844379172", and for "4210000001" result of "403242671" - cause as i found out, nibbles are in an inverted order at the output of fifo :)  Couple of questions here: 1) When i messed something with sync pulse (used it for wrreq pulses with not perfect conditions) i still got the pulse. But before that for a couple of clock cycles i got vertical lines - you could say that only a rising part of pulse. And thoses verical rising edges only were affecting the circuit.   Even if i had stuff like that in simulation - should i be worried ? It's just an infinitly short pulse (dirac pulse) - i can't have that in a real divice.  2) i downloaded and saw your modelsim example - quite nice but for now i'm just using quartus II + modelsim-altera.  Unfortunately when i wanted to see those q_fifo, fifo_data, shift_reg, rdusedw_fifo i had to put them into the top entity.   Can i see some signals inside the architecture ? and what's going on with them ?  I saw some names of the signals - i can choose them - but they are really crazy - strange names etc  3) So when i want to see some signal, i have to put it into entity, then put it into testbench (for component part of my tested entity and its instance - unit under test).  It's rather annoying. I read some where about defining your package - and putting there a record - then simply use this record in the enitity.  And then when i want to add some signal - i just change it in the package itself, and doesnt have to do the rest.  I tried to do that here - but when i wrote my package - i put it into used entity and into testbench (cause both have to see this record).  But then modelsim had some problems with this package - simulation couldn't start.   As i'm thinking now - perhaps it should be also compiled ?  4) Do you see here any issues for the actual device ? Can i easliy assume if data and clock recovery part is fine - my desing will work as the simulations suggests.  THANKS ONCE AGAIN madness

[Altera_Forum]

Are you doing a behavioral (aka RTL) or gate-level simulation?

[Altera_Forum]

Hi madness, 

 To see the internal signal names in the simulator, you need to use Modelsim to compile the source, and then all the names within the design are available. If you use Quartus to synthesize the design, and then simulate the output of Quartus, you lose the ability to probe the design internals.  I don't use Quartus to run Modelsim, so I'm not sure what options it has for RTL versus post-synthesis simulation. Look in the GUI for options that sound like these terms. Otherwise, use my example sim.tcl script as the basis for your own sim.tcl script for your design.  What do you mean when you say asynchronous 5/4b decoding? There is only one clock in your design, so I suspect you really mean combinatorial decoding. There's nothing wrong with that type of decoding. A timing analysis of the design will indicate whether there is too much delay through any combinatorial logic. You will get glitches from this type of logic, but so long as you register the outputs with the 125MHz clock, the timing analysis will check those paths.  Cheers, Dave

[Altera_Forum]

Hi, 

Yes Dave, i meant combinatorial :)  Rbugalho i'm doing gate-level simulation - don't really know how to do RTL simulation with quartus and modelsim-altera combined.  RTL simulation gives actual delay in a device?  madness

[Altera_Forum]

--- Quote Start ---   i'm doing gate-level simulation - don't really know how to do RTL simulation with quartus and modelsim-altera combined.   --- Quote End ---    Hopefully someone can provide details, as this is what you want to do to probe the internal signals.    --- Quote Start ---   RTL simulation gives actual delay in a device?   --- Quote End ---   No. You want to perform an RTL simulation to check your logic, and then once you are happy with it, you constrain your design using a TimeQuest .SDC file, synthesize it, and check that timing is met.  At that point, you can perform a gate-level simulation to confirm that your logic still operates correctly. This simulation can have logic delays in it added by synthesis, however, so long as your design has met timing, you don't really care too much about seeing those delays in the simulation.  Cheers, Dave

[Altera_Forum]

So it's essential that i in every project make my sdc file and constraint the design ? 

 how about smth like that:  create_clock -name clk_125_in -period 8 [get_ports {clk}] derive_clock_uncertainty derive_pll_clocks  Quartus wants more stuff to be constrained. Why else should i know about constraning ?  Should i for example constrain somehow my recovered clock from NRZI bitstream ?  regards madness

[Altera_Forum]

--- Quote Start ---  So it's essential that i in every project make my sdc file and constraint the design ?   --- Quote End ---    Yes.    --- Quote Start ---   how about smth like that:  create_clock -name clk_125_in -period 8 [get_ports {clk}] derive_clock_uncertainty derive_pll_clocks   --- Quote End ---    That is sufficient to constrain the internals of your design for operation with one input clock and PLL outputs, but it does nothing to constrain external signals.    --- Quote Start ---   Should i for example constrain somehow my recovered clock from NRZI bitstream ?   --- Quote End ---     Is there a clock, or is it really just a 125MHz pulse? If its a pulse generated in the 125MHz domain, then it is already constrained by the 125MHz clock constraint.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Rbugalho i'm doing gate-level simulation - don't really know how to do RTL simulation with quartus and modelsim-altera combined.  RTL simulation gives actual delay in a device?  --- Quote End ---    No, gate level simulation does that. :)  However, for development purposes, RTL simulation is faster and easier: you can see the internal signals of your code, not the internal signals of the synthesized result.  To perform RTL simulation in ModelSim is straightforward: instead of having ModelSim compile the .vo or .vho file synthesis produced, you have it compile the .v or .vhdl files you wrote.

[Altera_Forum]

--- Quote Start ---  Is there a clock, or is it really just a 125MHz pulse? If its a pulse generated in the 125MHz domain, then it is already constrained by the 125MHz clock constraint.  --- Quote End ---  It will be clock recovered from NRZI data - bit stream with no clock in one cable. The receiving module will recover the clock from the data - this 125 Mhz clock (different form the 125 Mhz from PLL and used in read part of fifo), and use this clock to put the data itself to shift register and to generate those wrreq pulses.  Next questions: 1) I haven't done quite good yet conditions for generating those fifo wrreq pulses, - when i try to do smth with that, sometimes i get:  https://sites.google.com/site/pauldab/home/spikes.jpg    the cursor is the actual sync detect, and i get those strange spikes - i tried to use the cursor to check if there's one near them or one them - but there are zero value in the spike.  Can i leave it like that if the rest of the circuit works ? do they have any real impact in the device?   Or it's rather not a good practic to leave smth like that - it suggests that the circuit is not perfect ?  2) when i compile a design i automatically get this in modelsim (included testbench in quartus options)  https://sites.google.com/site/pauldab/home/gate.jpg   Does vho suggests that in gate_level simulations i have actual delays from the device ?  I really don't see any any delays in my simulations - edges are perfectly aligned. In that view i click test_module_tb and then perform a simulation.  Should i before doing that use some options ?  best regards madness