Simulation problem with Avalon-MM clock crossing bridge

[bhunt]

Hi there, I'm using the avalon MM clock-crossing bridge with questasim. After generating the core in Quartus Prime, I compile it in questasim with no issues. However, in simulation, all of its output ports are stuck at X.

[Kenny_Tan]

Kindly take note that they will be some slowness on the first reply due to the public holiday, we will get back to you as soon as possible.

[SyafieqS]

Are you writing any testbench? mind to share it here the snippet? and also the snapshot in the questasim.

[bhunt · Accepted solution]

I found that the IP simulation model outputs X normally, after reset, until the first transaction is passed through it. Then the IP outputs stay non-X. 

[SyafieqS]

Understood. Any testbench written for this simulation? Mind to share here if there is any.

If there is any input value assigned to the input there should be a value outputted.

[SyafieqS]

May I know if there is any update from previous reply?

[SyafieqS]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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