Slip Ring Timing Recovery, PLL Question

[Altera_Forum]

I'm working on the design of a rotating camera whose frame valid and pixel clock go through slip rings. We've found that there can be glitches ranging from 10 ns to 10 us on both signals. The processor peripheral that the camera interfaces to can not handle abnormal (dropped) clock signals, so the signals have to contact the exact number of pixels / line and lines / frame else the video will be corrupted. One thought was to have a small FPGA use a PLL to maintain the 10.519 MHz clock, even if the pixel clocked dropped out for 10 us. Since frame valid could also have glitches, we could just use the first rising edge on frame valid to start internal counting and just count the PLL's output clock to recreate frame valid and generate a line valid.  

 http://www.alteraforum.com/forum/attachment.php?attachmentid=11988&stc=1    I created a project based around a MAX10, added an ALTPLL module, set up the PLL for source synchronous mode (so 10 bits of camera data would be phase synchronized with the PLL clock), and added a 12 MHz oscillator as a secondary clock that the PLL could use to (at least I hoped) generate the 10.519 MHz output if the PLL couldn't maintain lock on the pixel clock. Unfortunately, when I simulated this, it behaved nothing like I expected. I don't know how well the simulation attachment will show up, but what I end up getting is just the inclk1 input on the PLL output all the time.   My assumptions are clearly wrong about what the PLL can do, so I'd appreciate any recommendations on the best way to solve this problem. Thanks in advance for the help.

[Altera_Forum]

See [url]http://www.alteraforum.com/forum/showthread.php?p=213240 (http://www.alteraforum.com/forum/showthread.php?p=213240)[/URL]