Stratix 10 10GBASE-R with L-Tile/H-Tile Transceiver PHY

[BeB]

Hello,

I am trying to configure the L-Tile/H-Tile Tranceiver PHY IP for 10GBASE-R. I am following the user guide for documentation:

https://www.intel.com/programmable/technical-pdfs/683621.pdf

I find the recommendations of the user guide are somewhat contradictory and difficult to reconcile, and would appreciate some enlightenment on the following points.

First, as recommended, I am starting with the existing preset '10GBASE-R'.

- The PCS-PMA interface width is automatically set to 32 bits, so I should be pretty close to Figure 128 "Transceiver channel datapath and clocking for 10GBASE-R (PCS-PMA interface width = 32 bits)" on page 227

- In the IP configurator, the CDR reference clock frequency is set to 644.53125MHz, although figure 128 suggests it should be 322.265625MHz. Which one is it then?

- In section 2.5.3.1.1 "The XGMII Interface Scheme in 10GBASE-R" on page 230, it is stated that the interface to the fabric is 64-bit data / 8-bit control at 156.25MHz, but in the "Enhanced PCS" tab of the IP configurator, the field "FPGA fabric / Enhanced PCS interface width" is set to 66 bits. Should I change it to 64 bits?

- In section 2.4.2.5 "FIFO Operation for the Enhanced PCS" on page 131, it is stated that "In the 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO" and also that in phase compensation mode "The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency". Was that meant for the PCS FIFO, since the section concerns the Enhanced PCS and the TX Core FIFO is not part of it according to Figure 128?

- In section 5.2.1 "Transmitter Datapath" on page 362, in is stated that "In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin and PCS_clkout_x2(tx). In this mode, the read and write controls of the TX Core FIFO, can be driven by clocks from asynchronous clock sources but must be the same frequency with 0 ppm difference. You can use the FPGA fabric clock or tx_clkout (TX parallel clock) to clock the write side of the TX Core FIFO." Isn't the write side on the TX Core FIFO the XGMII data, and therefore clocked at 156.25MHz? Therefore it is implied that tx_coreclkin is the XGMII clock and therefore is also 156.25MHz? As a result, PCS_clkout_x2 is also 156.25MHz? (read and write side must be at the same frequency as stated above). Figure 128 seems to imply that tx_clkout could be either PCS_clkout (322.265625MHz) OR PCS_clkout_x2 (156.25MHz) but how can this be?

- In section 2.5.3.1.1 "The XGMII Interface Scheme in 10GBASE-R" on page 230, it is stated that "For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of TX phase compensation FIFO (PCS data) and the write clock of TX phase compensation FIFO (XGMII data in the FPGA fabric). [...] " The same section continues with: "This can be achieved by using the same reference clock as the transceiver dedicated reference clock input as well as the reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock.". What is the "dedicated reference clock input" in Figure 128? Is it the input to the ATX PLL at the bottom? Also this confirms that tx_coreclkin is the XGMII clock, correct?

Sorry for the long message, I really appreciate any light you may shed on these questions.

Regards,

BeB

[Kshitij_Intel · Accepted solution]

Hi,

Q1. The PCS-PMA interface width is automatically set to 32 bits, so I should be close to Figure 128 "Transceiver channel Datapath and clocking for 10GBASE-R (PCS-PMA interface width = 32 bits)" on page 227

Ans – Yes.

Q2. In the IP configurator, the CDR reference clock frequency is set to 644.53125MHz, although figure 128 suggests it should be 322.265625MHz. Which one is it then?

Ans- As you can see there are multiple options in the drop down menu for CDR reference clock frequency, you can choose any one but the preset is compliant with 10G Ethernet and the preset is configured in a way that we support 10G Ethernet. So If you add 10G Ethernet you may only 1-2 options to choose CDR reference clock.

Q3. In section 2.5.3.1.1 "The XGMII Interface Scheme in 10GBASE-R" on page 230, it is stated that the interface to the fabric is 64-bit data /8-bit control at 156.25MHz, but in the "Enhanced PCS" tab of the IP configurator, the field "FPGA fabric / Enhanced PCS interface width" is set to 66 bits. Should I change it to 64 bits?

Ans - In Enhanced PCS we have enabled TX and RX 64/66 Encoder. So it should be 66 if you choose 64 it will give error in ip parameter editor.

Q4. In section 2.4.2.5 "FIFO Operation for the Enhanced PCS" on page 131, it is stated that "In the 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO" and also that in phase compensation mode "The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency". Was that meant for the PCS FIFO, since the section concerns the Enhanced PCS, and the TX Core FIFO is not part of it according to Figure 128?

Ans- As per statement, the FIFO in the FPGA Fabric i.e., TX Core FIFO and RX Core FIFO.

-Q5. In section 5.2.1 "Transmitter Datapath" on page 362, in is stated that "In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin and PCS_clkout_x2(tx). In this mode, the read and write controls of the TX Core FIFO, can be driven by clocks from asynchronous clock sources but must be the same frequency with 0 ppm difference. You can use the FPGA fabric clock or tx_clkout (TX parallel clock) to clock the write side of the TX Core FIFO." Isn't the write side on the TX Core FIFO the XGMII data, and therefore clocked at 156.25MHz? Therefore, it is implied that tx_coreclkin is the XGMII clock and therefore is also 156.25MHz? As a result, PCS_clkout_x2 is also 156.25MHz? (Read and write side must be at the same frequency as stated above). Figure 128 seems to imply that tx_clkout could be either PCS_clkout (322.265625MHz) OR PCS_clkout_x2 (156.25MHz) but how can this be?

Ans- Need to check on this, but the IP is very old, trusted and stable. So, I do not have any doubt on that It is taking the 10G- BASE compliant configuration.

Q6. In section 2.5.3.1.1 "The XGMII Interface Scheme in 10GBASE-R" on page 230, it is stated that "For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of TX phase compensation FIFO (PCS data) and the write clock of TX phase compensation FIFO (XGMII data in the FPGA fabric). [...] " The same section continues with: "This can be achieved by using the same reference clock as the transceiver dedicated reference clock input as well as the reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock.". What is the "dedicated reference clock input" in Figure 128? Is it the input to the ATX PLL at the bottom? Also, this confirms that tx_coreclkin is the XGMII clock, correct?

Ans- Yes. I think this clear your doubt in Q5 as well.

Thank you

Kshitij Goel

[BeB]

Thank you very much for the detailed answer, very much appreciated!

BeB

[Kshitij_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you

Kshitij Goel