Programmable Devices
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VHDL Counter

Kris4
Novice
456 Views

Hi,

 

I'm trying to make an automatic 7-bit up and down counter. I want it to be in a loop. Let' say it counts from zero to 128, then back to zero, and so on . Is it possible to make a counter that starts counting from for example 40 and counts to 50 ?  

 

I look forward to Your help

Thanks

 

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1 Solution
RichardTanSY_Intel
397 Views

Not a fan of schematic design, I always recommend users to use verilog or VHDL to design their project.

Anyhow, you might need to alter a bit of the vhdl template by removing the min_count and max_count. And define the range in the vhdl design.

So that when you convert it into the bdf, it will shown as q[7..0] instead of q[mincount...maxcount]. I guess bdf only recognize it when it is in number.

Took some time to figure it out and attached here a working design with range 40 to 140 so you can check it out.

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

 

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11 Replies
RichardTanSY_Intel
443 Views

I believe I have help you on a similar question:

https://community.intel.com/t5/Programmable-Devices/VHDL-logical-block/m-p/1428085#M87663

 

You can get the up-down counter design in the same way:

  1. You may use the Counter VHDL template provided in the Quartus tool itself. Insert template> VHDL > Full Design > Arithmetic > Counter > Binary Up/Down Counter.
  2. Change the MIN_COUNT and MAX_COUNT to your desired range, and you should be able to set the counter range.

Is the design template not working as you intended?

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

 

 

Kris4
Novice
426 Views

Hi,

 
Indeed I found it but I have warnings with the output saying can't find the node source.
What should I put on the output of this counter?
 
Thnks
sstrell
Honored Contributor III
420 Views

What is the exact warning you are getting and can you show your code?

Kris4
Novice
414 Views

So this is the message, I don't know since I'm begginer to it what to put on the output bus so to make it work and be able to analyze it in simulations.

The code is the same (from the template binary up down counter)

 

 

 

 

int.PNG

RichardTanSY_Intel
398 Views

Not a fan of schematic design, I always recommend users to use verilog or VHDL to design their project.

Anyhow, you might need to alter a bit of the vhdl template by removing the min_count and max_count. And define the range in the vhdl design.

So that when you convert it into the bdf, it will shown as q[7..0] instead of q[mincount...maxcount]. I guess bdf only recognize it when it is in number.

Took some time to figure it out and attached here a working design with range 40 to 140 so you can check it out.

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

 

RichardTanSY_Intel
385 Views

May I know does my latest reply helps?

 

Best Regards,

Richard Tan

 

Kris4
Novice
373 Views

Great It almost helped . I just wonder if it is possible to make it loop itself no matter of the inputs . So its' a closed cycle. 40->140->40 and so on. Nonetheless thanks for helping!

 

 

RichardTanSY_Intel
329 Views

Yes, it is possible.

Probably need to add a few if-else statement so that the counter count down when get to max_count and count up again when reach min_count.


Best Regards,

Richard Tan


RichardTanSY_Intel
320 Views

Do you have further question in regards to this case?


Best Regards,

Richard Tan


RichardTanSY_Intel
300 Views

I believe I have provided the necessary information/answer to your inquiries, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


FJ_Robert
Beginner
230 Views

Hi, I've started today in this community.

I see your question as a good example project for our students. We've been systematically implementing counters using VHDL for many years for our CSD course at DIGSYS. Browse our P7 projects on standard synchronous registers and counters.

To invent your 7-bit binary counter modulo 128, we will name it Counter_mod128, we have several options:

- We can chain two universal 4-bit binary counters components that we name Counter_mod16 using terminal counts and count enable control signals. This is what we call our "plan C2". This is multiple file VHDL project.

- We can invent it as FSM using arithmetic libraries and defining state signals STD_LOGIC_vectors. This is what we call our "plan Y" for large binary counters. This project is a single VHDL file, because even if the FSM has a hierarchy of internal processes or components we place them all as processes in the same VHDL file.

We can adjust the final state count as you say in the range from 40 to 50 using counter truncation techniques. We explain truncation and expansion concepts in this lecture L7.3.

 

regards,

Francesc J. Robert

 

 

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