Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20754 Discussions

What's the parameter 'pfd_clk_select'?

Altera_Forum
Honored Contributor II
915 Views

Today, I built a new QuartusII project. The project include two ALT2GXB block, I don't assign the pins. When I compile this project. Quartus point out a error : 

 

Error: WYSIWYG primitive "channel_quad[0].pll0" has CLK[2] port that must be connected because parameter pfd_clk_select is set to 2 

 

What's the parameter pfd_clk_select? How to solve it? 

 

Thank you!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
223 Views

If the ALT2GXB pll_clk port miss source or has a wrong source, Quartus will show this error. 

 

But I don't know what's the parameter pfd_clk_select mean?
0 Kudos
Reply