Why do i get this error when I use lvds?

[MinzhiWang]

Hello guys,

My device is 10CX220YF780E5G and the Quartus is QPP23.4. I implemented one channel LVDS receiver in my project. External PLL was checked. After full complilation, I found LVDS module was optimaized away. So I constrained LVDS output data to FPGA output pins. Then I got the following error. Can anyone tell me what blocks me to use lvds? 

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (12677): No exact pin location assignment(s) for 38 pins of 45 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS_CLOCK_TREE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
	Error (175020): The Fitter cannot place logic LVDS_CLOCK_TREE that is part of LVDS SERDES Intel FPGA IP LVDS_1Ch6B_RX_altera_lvds_2001_3ymtrna in region (38, 32) to (38, 32), to which it is constrained, because there are no valid locations in the region for logic of this type.
		Info (14596): Information about the failing component(s):
			Info (175028): The LVDS_CLOCK_TREE name(s): u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst
		Error (16234): No legal location could be found out of 2 considered location(s).  Reasons why each location could not be used are summarized below:
			Info (175013): The LVDS_CLOCK_TREE is constrained to the region (38, 32) to (38, 32) due to related logic
				Info (175015): The I/O pad clkin is constrained to the location PIN_AA18 due to: User Location Constraints (PIN_AA18) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 19
				Info (14709): The constrained I/O pad drives a IOPLL, which drives this LVDS_CLOCK_TREE
			Error (175006): There is no routing connectivity between the LVDS_CLOCK_TREE and destination LVDS_CHANNEL
				Info (175027): Destination: LVDS_CHANNEL u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|channels[0].rx_non_dpa.serdes_dpa_inst~CHANNEL
					Info (175015): The I/O pad M10_TO_C10_LVDS_RX is constrained to the location PIN_P3 due to: User Location Constraints (PIN_P3) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 29
						Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL
				Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements
				Info (175021): The destination LVDS_CHANNEL was placed in location LVDS_CHANNEL containing P3
				Info (175029): 2 locations affected
					Info (175029): LVDSCLOCKTREE_X38_Y32_N4
					Info (175029): LVDSCLOCKTREE_X38_Y32_N5
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 7 errors, 2 warnings
	Error: Peak virtual memory: 1397 megabytes
	Error: Processing ended: Mon Jul 29 17:45:25 2024
	Error: Elapsed time: 00:00:09
	Error: System process ID: 12428

It seems that I violated some limitation of lvds application. However, I don't know what limitation I have violated.

[AqidAyman_Intel]

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[AqidAyman_Intel]

Hello,

Can you try to change the pin assigned for the dedicated clock input to be in the same bank as the LVDS channel pin?

Kindly confirm back if this suggestion is working or not.

Thanks.

[MinzhiWang]

Hello Aqid,

Thanks for you reply this post.

This issue happened just as I made one simple project for LVDS test and trying. Now we try internal PLL, instead of external PLL, the LVDS function looks fine.

As you mentioned to try clock input, as following images, we already try this to receiver external ADC output.

However, here i have another question about LVDS need you help. Which is of LVDS constrain. We know that LVDS needs input termination and with the value of "Differential", as above image. We applied this constrain for ADC output pairs. They run well.

So we have another type  LVDS pairs input, which are not from external ADC chips. They come from comparator devices output. FPGA use differential I/O pairs to receiver them. When we apply same constrain as ADC output pairs, they can't run well. The comparator output run as pulse signal, we can use Signaltap to monitor its signal quality. It's very bad under this constrain.

But they can run well when On-Chip Termination for Transceiver Rx pin (with 100 ohms value)constrains were applied to them. My question is what's the different between them?

[AqidAyman_Intel]

If transceiver termination settings are applied to GPIO pins configured as LVDS, the assignment should be ignored. Check the fitter reports to confirm. There should be an ignored assignments (or I/O assignment warnings) report, and you can look at the input pins report to see which, if any, input termination is used.

Assuming the assignment is ignored and there is no input termination on the LVDS pins used for the comparator, then my guess is the signal has a low voltage swing. When termination is enabled, it will reduce the voltage swing, so if the swing is already low, enabling termination may reduce the VID too much for the receiver to operate properly. 

[MinzhiWang]

Hi Aqid,

Yes, you're right. The tranceiver termination settings are ignored.

If this is the case, the differential pairs interconnection have no termination configurations. How to ensure the circuit run well?

I check C10GX datasheet, lvds vid only have min requirement as 100mV. So I have the the external input signal swing range. The comparator output doesn't drive to FPGA directly. Compartors otuput drive OR gate firstly, then OR gates outputs drive to FPGA's lvds receivers. The OR gates otuput signals are CML pairs. We use DC coupling, so they connected directly. The OR gate output signal swing is much higher enough than FPGA lvds VID requirement, 100mV, as following imgae:

The OR gate output signal was measured as following,

So we think we may apply fpga interanl termination for lvds receiver.

[AqidAyman_Intel]

What is the significance of the blue trace in the scope shot? 

Although we agree the Vid min is satisfied, we can’t tell the common mode voltage of the differential signal. It must also be in the supported common mode range of the Cyclone 10 GX LVDS receiver. There is mention of Voh on the CML datasheet indicating it is near VCC which is either 2.5V or 3.3V, so this is above our common mode range.

[MinzhiWang]

Hi,

1. The bottom blue line signal is just of the oscilloscope's reference to trace the object pulse.

2. You're right, I check the hardware again. The connection between OR gate's CML output and FPGA lvds receiver input under AC coupling. In this case, we still have above issue. That's we can't enable the on-chip termination.

Do we nned other extra outside pull-up and/or pull-down resistors?

Thanks

[AqidAyman_Intel]

I also agree differential termination should be used, but it is up to you to figure out what is stable for your system. If you don’t use on-chip termination and it is working okay on this board, I can understand you may have concern for building a larger volume of boards and it continuing to be stable. It “should” work with on-chip differential termination.

Technically, the general purpose I/O pins do not support CML, that is typically a standard used with the transceivers with AC coupling.

[AqidAyman_Intel]

Hello,

Okay, if it’s AC coupled, then it will need DC restoration resistors on the board. The GPIO and dedicated clock pins in our devices do not have DC biasing capability and require external circuitry when AC coupling. The transceivers have the required termination and biasing circuits to support AC coupling.

Here is an example from the Cyclone 10 GX Handbook that shows AC coupling with the DC restoration circuit. VICM can be set with a voltage divider or power supply, typical values used by customers is 1.2V or 1.25V. Then the two 50 Ohm resistors serve as the DC bias connection and 100 Ohm differential termination:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/lvpecl-termination.html

Thanks.

[MinzhiWang]

Hi Aqid,

Thanks for you info above. There are two things which need to confirm with you.

1.  Your provided example is of external LVPECL drives FPGA LVPECL I/O. You know, our case is of external CML drives FPGA LVDS I/O. Can we use the same structure of the example in our case?

2. If item 1's answer is "Yes". According to your comments "Then the two 50 Ohm resistors serve as the DC bias connection and 100 Ohm differential termination", after using this structure, the LVDS receiver's inside differential OCT should not need to be used any more?

Thanks

[AqidAyman_Intel]

Hi,

1. Yes, the example for LVPECL is applicable to any AC coupled interface to the GPIO and dedicated clock input pins. This is just one circuit example, there are other ways to do it. Some customers use a 5 resistor solution which has a pull up and pull down on each of the p and n legs, then a 100 Ohm differential termination. You can find that example in the Stratix II handbook. The example from the Cyclone 10 GX handbook is an implied 4 resistor solution where Vicm is created with a voltage divider. If you happen to have a 1.2V or 1.25V supply on the board, you wouldn’t need the voltage divider resistors and then it would just be a 2 resistor solution (the two 50 Ohm resistors).
2. Correct, when implementing these external biasing schemes, you would not use on-chip differential termination.

Hope this info helps to clarify you. Thanks.

[MinzhiWang]

Hello Aqid,

Thanks for you information.

Can you give me the link for Stratix II? I have Stratix II device datasheet long time ago. I checked this datasheet, however, I couldn't fine the similar information as your above link of Cyclone 10 GX device.

Thnaks

Best Regard

[AqidAyman_Intel]

Hello,

Refer to the link below for the Stratix II Handbook:

https://www.intel.com/content/www/us/en/content-details/654261/stratix-ii-device-handbook.html?wapkw=stratix%20ii%20handbook&DocID=654261

Regards,

Aqid

[MinzhiWang]

Hi Aqid,

I have this datasheet in my computer, however, I can't find the example as Cyclone 10 GX which you provided previously. As following image:

Are sure  the similar examples can be found in Stratix II datasheet?

Thanks 

Best Regard

[FvM]

Hi,

would you mind to specify the actual problem clearly? As far as I understand it's about CML received by Cyclone 10 GX? Do you need DC coupling (input signal is not DC-free, e.g. unencoded data stream) or not? What's the signal source, CML level specifications of devices are slightly different.

Whats's the relation to Stratix II?

[MinzhiWang]

Hi FvM,

Thanks for you follow this post.

1. The primary problem of this post is that I can't apply "on-chip differential termination" constrain for my LVDS receiver. Becasue the receiver output signal will be distorted. The input CML signal is received by FPGA's LVDS receiver. It's single bit pulse signal. We need  this pulse signal in our following logic design. This pulse signal will be hided in mass noise when "n-chip differential termination" constrain is used. So we went to use tranceiver Rx pin constrain. And the pulse could be recognized after that. But Aqid told me that this constrain should be ignored by Quartus. He's right, we have check the compilation report carefuly. So in this case, we could recognize this pulse without any on-chip constrain.

2. The CML differential signal outputed from OR gate logic chip. So it should be of data stream. This sinlge bit signal just gather random pulse signal. FPGA logic need to receive and reconize it correctly.

3. Our hardware engineer have already reserved AC/DC coupling and outside pull up/down resistor options. We can switch to select what option we want.

4. If outside AC coupling used, Aqid give me above examples of LVPECL TO LVPECL in Cyclone 10 GX. And also he said if I want to refer similar example of LVDS receiver, i can check and refer from Stratix II datasheet. Unfortunately, i can't fine this kind of example from Stratix II datasheet.

That's all of my problem. I hope that i explain clearly.

Thanks

Best Regard

[AqidAyman_Intel · Accepted solution]

Hi,

Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.

Let me know if you can't find it.

Regards,

Aqid

[MinzhiWang]

Hi Aqid,

Sorry, I mis-understand you, I expected to search the example of LVDS. Now I get the LVPECL AC coupling termination example from Stratix II datasheet.

Thanks 

Best Regard

[AqidAyman_Intel]

Hello,

No worries. I'm glad you found it.

Regards,

Aqid

[AqidAyman_Intel]

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