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Do you get unexpected results while the parameter changes or continuously?
Trivial question, is the design fully constrained and meets timing?
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Thank you for your reply.
Changing the parameter indeed made a difference. The final result is obtained by subtracting the measured circuit delay from this parameter. After the circuit was programmed, I thought the circuit delay would not change anymore. However, transmitting data via serial port actually caused a significant change in the measured circuit delay. I imposed very few restrictions or timing requirements, but I believed that the circuit would not change after programming
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Hi student8,
From my understanding, I think it is expected, while sending data from a serial port to an FPGA can impact timing, careful design considerations, proper clock domain crossing techniques, and appropriate buffering can help mitigate potential timing issues and ensure reliable communication between the serial device and the FPGA.
Regards,
Fakhrul
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