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Will sending data from serial port to FPGA change the existing layout

student8
Novice
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I designed a module that uses direct counting to measure signal delay through a circuit. One of the parameters is stored in a register and assigned using an external serial port. I used signal tap to capture the measurement results of circuit delay and found that without re burning, the measurement results of circuit delay were stable (with fluctuations not exceeding my measurement accuracy). But later it was found that modifying this parameter through the serial port would affect the measured circuit delay results, and the magnitude of the change would be huge, reaching more than 10ns (I think even considering the temperature effect is too large). May I ask what may be the reason for this and how can we explain this phenomenon from the underlying structure? This module is a part of the company's project, and I cannot directly send out the code. Please forgive me.
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FvM
Valued Contributor III
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Do you get unexpected results while the parameter changes or continuously?

 

Trivial question, is the design fully constrained and meets timing?

student8
Novice
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Thank you for your reply.

Changing the parameter indeed made a difference. The final result is obtained by subtracting the measured circuit delay from this parameter. After the circuit was programmed, I thought the circuit delay would not change anymore. However, transmitting data via serial port actually caused a significant change in the measured circuit delay. I imposed very few restrictions or timing requirements, but I believed that the circuit would not change after programming

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Fakhrul
Employee
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Hi student8,


From my understanding, I think it is expected, while sending data from a serial port to an FPGA can impact timing, careful design considerations, proper clock domain crossing techniques, and appropriate buffering can help mitigate potential timing issues and ensure reliable communication between the serial device and the FPGA.


Regards,

Fakhrul


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Fakhrul
Employee
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