I have the following code but after compiling it said there is error in conv_std_logic_vector , can someone help me ??library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity QuadratureDecoder is Port ( QuadA : in STD_LOGIC; QuadB : in STD_LOGIC; Clk : in STD_LOGIC; Position : out STD_LOGIC_VECTOR (7 downto 0)); end QuadratureDecoder; architecture Behavioral of QuadratureDecoder is signal QuadA_Delayed: STD_LOGIC_VECTOR(2 downto 0) := "000"; signal QuadB_Delayed: STD_LOGIC_VECTOR(2 downto 0) := "000"; signal Count_Enable: STD_LOGIC; signal Count_Direction: STD_LOGIC; signal Count: STD_LOGIC_VECTOR(7 downto 0) := "00000000"; begin process (Clk) begin if Clk='1' and Clk'event then QuadA_Delayed <= (QuadA_Delayed(1), QuadA_Delayed(0), QuadA); QuadB_Delayed <= (QuadB_Delayed(1), QuadB_Delayed(0), QuadB); if Count_Enable='1' then if Count_Direction='1' then Count <= Count + 1; Position <= conv_std_logic_vector(Count, 8); //compile wrongly else Count <= Count - 1; Position <= conv_std_logic_vector(Count, 8); //compile wrongly end if; end if; end if; end process; Count_Enable <= QuadA_Delayed(1) xor QuadA_Delayed(2) xor QuadB_Delayed(1) xor QuadB_Delayed(2); Count_Direction <= QuadA_Delayed(1) xor QuadB_Delayed(2); end Behavioral;
You are using CONV_STD_LOGIC_VECTOR to convert a std_logic_vector to a larger std_logic_vector. This is not what CONV_STD_LOGIC_VECTOR is for.CONV_STD_LOGIC_VECTOR is for converting integers into std_logic_vectors. My advice is:
- Do not use numeric_std, std_logic_unsigned and std_logic_arith in the same design unit. They are all there to do the same job, two of them both declare "signed" and "unsigned" datatypes, and (in some cases) they conflict with each other. IMHO, remove std_logic_arith and std_logic_unsigned, and stick with just numeric_std.
- The quickest way to do the conversion you're looking for is:
Position <= std_logic_vector(resize(unsigned(Count), 8));This is assuming that you go for my suggestion of using numeric_std.
- A slightly slower, but neater, solution would be to declare "Count" as "unsigned" (from numeric_std), and then you would only need:
Position <= std_logic_vector(resize(Count, 8));
Positiion and count both have length 8, so whats wrong with just:Position <= count; ? But you should be using numeric_std. Std_logic_unisnged is not part of the IEEE VHDL Standard.
Oops, as Tricky pointed out, they're actually the same size. For some reason, when I read your code, I thought that "Position" was a larger vector.However, you still would be better off getting rid of std_logic_arith and std_logic_unsigned. If you declare "Count" as UNSIGNED, then your assignment would just be:
Position <= std_logic_vector(Count);