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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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internal weak pull-high of CPLD and FPGA

Altera_Forum
Honored Contributor II
‎07-05-2017 08:42 AM
1,512 Views

Hi All, 

I use CPLD(EPM240Z) and FPGA(EP4CE30F23C8N) in my design. 

Whenever the device is not in user mode all I/O are tri-stated.But there are internal weak pull up, how can cancel pull up ? 

Thank you.
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Altera_Forum
Honored Contributor II
‎07-05-2017 12:16 PM
558 Views

Internal pull-ups in not configured state can't be disabled. 

 

The usual way to reflect it is to use logic high as inactive, safe state of connected hardware (all outputs off etc.). If not possible, use external pull-down resistors to override the weak pull-ups e.g. 470R to 1K for critical signals.
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