problem in interfacing

Altera_Forum · ‎11-25-2014

Hi all,

can any one suggest me how to interface altera cyclone 3 fpga starter kit( EP3C25F324 ) and ti daughter card ( SDALTEVK/NOPB ). i have both boards. when i see both schematic diagram then find some of pins iof HSMC not matched together ( like:- HSYNC , ODDEVEN, VFORMAT etc.). so plz suggest how to interface together.

it is possible to interface both devices ??

if no then which device configure to SDALTEVK/NOPB.

Altera_Forum · ‎11-25-2014

Refer to your other thread: http://www.alteraforum.com/forum/showthread.php?t=46923 (http://www.alteraforum.com/forum/showthread.php?t=46923)

Altera_Forum · ‎11-27-2014

hello,

thanks for the reply bt i find some problem in pin planner, when i put hsync,vformate,tx_clk in data and clock out location then it don't support and give a error. and i also change voltage level to 1.8 volt bt it don't work and give error. so what i do.

Altera_Forum · ‎11-27-2014

I've had a quick look at the schematics - I can't see an issue.

HSYNC_P/N are driven from the SDALTEVK board to FPGA pins G17/G18 - OK

VFORMAT_P/N are driven from the SDALTEVK board to FPGA pins T3/R3 - OK.

TX1_CLK_P/N need to be driven from the FPGA from pins H17/H18 - OK.

Specify all the above IO standards as LVDS and all should be fine. All the above FPGA pins can be use as required by these signals.

Cheers,

Alex

Altera_Forum · ‎11-27-2014

i am getting issue like Error (169079): Pad 143 of non-differential I/O pin 'TX2_SDA' in pin location L17 is too close to pad 140 of differential I/O pin 'tof_n' in pin location M17 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.

Altera_Forum · ‎11-27-2014

and also give the location for altera_reserved_tms, altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck . more issue is to understand the right pins for ek signal.

Altera_Forum · ‎11-27-2014

Quartus assumes the single ended signal is going to cause interference on the differential signal because it's too close.

Add an 'io_maximum_toggle_rate "0mhz"' attribute to any non-differential signals in that bank. Do this as follows:

In the 'Pin Planner', find the relevant signal - 'TX2_SDA'. In the 'Toggle Rate' column, enter 0 (zero). Do this for any non-differential signal in the same bank as 'tof_n'. If you can't see the 'Toggle Rate' column, right click anywhere in the column headings and select 'Customise Columns...', find 'Toggle Rate' in the 'Available columns:' box and add it to the visible columns.

The JTAG signals (TMS, TDO etc.) are reserved pins - you don't need to assign them.

I don't understand what you mean by the 'ek' signal.

Cheers,

Alex

Altera_Forum · ‎12-15-2014

i got this error plz resolve it :-

Error (176172): Can't place node "hsync_n" -- node is a differential I/O node

it is placed at G18 and fitter location shows E1.

Altera_Forum · ‎12-15-2014

if i assigned hsync_n to E1 location, this error comes again. i dont know why this error comes. i compile my design before many times but this error comes today. plz help me to resolve this error.

Altera_Forum · ‎12-15-2014

If, as you say, it worked before you'll have to work out what it is you've changed to break it...

Have you added any other constraints? There are plenty of conflicting constraints you could add that would stop Quartus from being able to use the pin you've selected. Have you accidentally removed the 'IO_MAXIMUM_TOGGLE_RATE "0MHz"' settings?

Cheers,

Alex

Altera_Forum · ‎12-15-2014

i dont know about that, last night i can done my configuration bt some pins like, tx_clk_out n,p, vformate and some more pins location i can change today and when i compile my design i got this error. if i again move back to all pin location then this error never resolve. if you know about that plz tell me.

where i found this setting because i dont know about Quartus 2 software. i am working 1st time in altera's Fpga.

Altera_Forum · ‎12-17-2014

HELLO SIR, NO ACTION IS DONE WHEN I APPLY IO_MS_TOGGLE_RATE TO 0 MHz. SO ANY OTHER SOLUTION PLZ PROVIDE ME.

Altera_Forum · ‎12-17-2014

i give you full detail of pin location, for your more understanding.

altera_reserved_tck Input 2.5 V (default) 8mA (default)

altera_reserved_tdi Input 2.5 V (default) 8mA (default)

altera_reserved_tdo Output 2.5 V (default) 8mA (default) 2 (default)

altera_reserved_tms Input 2.5 V (default) 8mA (default)

clkin_50 Input PIN_A9 8 B8_N0 1.8 V 8mA (default)

CLKOUT_SMA Output PIN_A1 8 B8_N0 1.8 V 8mA (default) 2 (default)

DIPSW[7] Input PIN_H15 6 B6_N0 2.5 V 8mA (default)

DIPSW[6] Input PIN_D17 6 B6_N0 2.5 V 8mA (default)

DIPSW[5] Input PIN_H13 6 B6_N0 2.5 V 8mA (default)

DIPSW[4] Input PIN_D18 6 B6_N0 2.5 V 8mA (default)

DIPSW[3] Input PIN_C17 6 B6_N0 2.5 V 8mA (default)

DIPSW[2] Input PIN_M5 2 B2_N0 2.5 V 8mA (default)

DIPSW[1] Input PIN_P18 5 B5_N0 2.5 V 8mA (default)

DIPSW[0] Input PIN_R16 5 B5_N0 2.5 V 8mA (default)

freerun Output PIN_T17 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

genlock_no_lock Input PIN_M6 3 B3_N0 2.5 V 8mA (default)

genlock_no_ref Input PIN_M13 4 B4_N0 1.8 V 8mA (default)

hsync_n Input PIN_E1 1 B1_N0 1.8 V 8mA (default) 0 MHz

hsync_p Input PIN_E2 1 B1_N0 2.5 V 8mA (default) 0 MHz

I2C_SCL Bidir PIN_N16 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

LED[7] Output PIN_E9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[6] Output PIN_C9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[5] Output PIN_E10 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[4] Output PIN_D9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[3] Output PIN_N9 3 B3_N0 1.8 V 8mA (default) 2 (default)

LED[2] Output PIN_N12 4 B4_N0 1.8 V 8mA (default) 2 (default)

LED[1] Output PIN_P12 4 B4_N0 1.8 V 8mA (default) 2 (default)

LED[0] Output PIN_P13 4 B4_N0 1.8 V 8mA (default) 2 (default)

oddeven_n Input PIN_L18 5 B5_N0 2.5 V (default) 8mA (default)

oddeven_p Input PIN_K18 5 B5_N0 2.5 V (default) 8mA (default)

PBSW[3] Input PIN_B10 7 B7_N0 1.8 V 8mA (default)

PBSW[2] Input PIN_A10 7 B7_N0 1.8 V 8mA (default)

PBSW[1] Input PIN_F2 1 B1_N0 2.5 V 8mA (default)

PBSW[0] Input PIN_F1 1 B1_N0 2.5 V 8mA (default)

pll_clk_n Input PIN_F18 6 B6_N0 2.5 V (default) 8mA (default)

pll_clk_p Input PIN_F17 6 B6_N0 2.5 V (default) 8mA (default)

PLL_SDA Bidir PIN_N11 4 B4_N0 1.8 V 8mA (default) 2 (default)

rst_n Input PIN_R17 5 B5_N0 2.5 V (default) 8mA (default)

RX1_SDA Bidir PIN_N15 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

rx_clk_n Input PIN_N18 5 B5_N0 2.5 V (default) 8mA (default)

rx_clk_p Input PIN_N17 5 B5_N0 2.5 V (default) 8mA (default)

rx_d_n[4] Input PIN_P1 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[3] Input PIN_L3 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[2] Input PIN_L5 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[1] Input PIN_H1 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_n[0] Input PIN_C1 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_p[4] Input PIN_P2 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[3] Input PIN_L4 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[2] Input PIN_K5 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[1] Input PIN_H2 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_p[0] Input PIN_C2 1 B1_N0 2.5 V (default) 8mA (default)

sdi_ck_en1 Output PIN_J13 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

sdi_ck_sel0 Output PIN_H16 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

sdi_ck_sel1 Output PIN_N10 4 B4_N0 1.8 V 8mA (default) 2 (default) 0 MHz

tof_n Input PIN_M17 5 B5_N0 2.5 V (default) 8mA (default)

tof_p Input PIN_L16 5 B5_N0 2.5 V (default) 8mA (default)

TX1_SDA Bidir PIN_E17 6 B6_N0 2.5 V (default) 8mA (default) 2 (default)

TX2_SDA Bidir PIN_H17 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

tx_clk_n Output PIN_D1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_clk_p Output PIN_D2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[4] Output PIN_M1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[3] Output PIN_L1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[2] Output PIN_K1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[1] Output PIN_G1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[0] Output PIN_B1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[4] Output PIN_M2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[3] Output PIN_L2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[2] Output PIN_K2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[1] Output PIN_G2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[0] Output PIN_B2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

vformat_n Input PIN_R1 2 B2_N0 2.5 V (default) 8mA (default)

vformat_p Input PIN_R2 2 B2_N0 2.5 V (default) 8mA (default)

Altera_Forum · ‎12-17-2014

Can you (are you happy to) post the .qsf file for the project? You'll find it in the same directory as the Quarus project (.qpf) file...

Altera_Forum · ‎12-17-2014

hello Sir,

plz tell me, what i do to resolve this error, and i know i did mistake but i dont know what i do. plz help me.

Altera_Forum · ‎12-18-2014

TO_BE_DONE

Altera_Forum · ‎12-19-2014

hello Sir,

in the zip file you can find the altera_vhd.qsf file.

Altera_Forum · ‎12-19-2014

OK - I can basically make your Quartus Settings File (qsf) file work. However, can you confirm you're still using the Cyclone III Dev kit you mentioned in your first post?

If so, the qsf you sent is specifying the wrong device. That kit features a Cyclone III EP3C25F324. Your settings file calls up an EP3C120F780.

You've also previously referred to "hsync_n" and it being placed at E1 or maybe G18. Your project settings are trying to put it on L1...?

So, I think you have a little work to do. There a quite a few inconsistencies with all the info you've posted. Go over the project's settings thoroughly and make sure you're happy that you have the right device and pinout.

Cheers,

Alex

Altera_Forum · ‎12-19-2014

hello sir,

i am upload wrong .qsf file,

in this post you can find the correct .qsf file in the Zip folder. i m sorry for this.

Altera_Forum · ‎01-05-2015

Are you still having problems with this?

A quick look at the .qsf you posted shows a conflict between the 'hsync_p' & 'hsync_n' signals. One is 1.8V, the other 2.5V.

I think you should be generating hsync as a differential signal. However, your qsf shows different single ended I/O standards for each half of the pair.

If you still need help let me know.

Happy New Year,

Alex