About Caching Home agent Register address in Xeon max server

[fei1234567]

Hi,

I am trying to reproduce a code on my machine, I encountered variables related to the CHA  hardware register. However, after reviewing the Intel IA32 manual, I was unable to find any reference to the CHA hardware register address.

Could you kindly clarify where you obtained the value for this variable or provide some guidance on how to access the CHA register values? Any insights would be greatly appreciated.

Thank you!

Here is code based on skylerk

// CHA counters are MSR-based.

// The starting MSR address is 0x0E00 + 0x10*CHA

// Offset 0 is Unit Control -- mostly un-needed

// Offsets 1-4 are the Counter PerfEvtSel registers

// Offset 5 is Filter0 -- selects state for LLC lookup event (and TID, if enabled by bit 19 of PerfEvtSel)

// Offset 6 is Filter1 -- lots of filter bits, including opcode -- default if unused should be 0x03b, or 0x------33 if using opcode matching

// Offset 7 is Unit Status

// Offsets 8,9,A,B are the Counter count registers

#define CHA_MSR_PMON_BASE 0x0E00L

#define CHA_MSR_PMON_CTL_BASE 0x0E01L

#define CHA_MSR_PMON_FILTER0_BASE 0x0E05L

// #define CHA_MSR_PMON_FILTER1_BASE 0x0E06L // No FULERT1 on Icelake

#define CHA_MSR_PMON_STATUS_BASE 0x0E07L

#define CHA_MSR_PMON_CTR_BASE 0x0E08L

[McCalpinJohn]

The performance counters for the CHA (and for other units outside of the cores) are documented in the "uncore" performance monitoring reference manual.

For SKX, the manual is Intel document 336274 "Intel Xeon Processor Scalable Memory Family Uncore Performance Monitoring Reference Manual".    Different manuals exist for each generation of Intel servers.  Each has a section in Chapter 1 called "Addressing Uncore PMON State" that includes information about the MSR addresses used for the CHA hardware performance counters.  In most cases there is a full table of the MSR numbers used for control and count registers for each CHA number.