Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Disabling particular llc slices?

New Contributor I

I have a Sapphire Rapids processor, Xeon 6430 gold. I am running my whole system in sub-numa clustering mode, and I would like to disable particular last level slices (LLCs) in my system if possible. For instance, I would like to disable LLCs for core 0--7, is there any ways to do so? 


I have tried to do this via Intel cache allocation technology (via pqos) and also model-specific registers (MSR), both of which try to control cache ways. However, I find it is not allowed to set the cache ways to complete 0, (e.g., "sudo wrmsr -p 0 0xC90 0x0000"). Are there any other ways to fully disable specific LLCs?


Thank you.

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4 Replies

Hello huangwentao,


Thank you for posting in the community!


To ensure you receive the most specialized assistance, we have a dedicated forum that addresses these specific concerns. Therefore, I will be moving this discussion to our Server Forum. This will allow our knowledgeable community and experts to provide you with timely and accurate solutions.


Best regards,

Norman S.

Intel Customer Support Engineer

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New Contributor I

Hi Norman,


Please help move it to Server Forum, thank you.



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Honored Contributor III

I don't recall seeing any Intel features that allow enabling/disabling L3 cache slices in any of the mesh-based processors.

None of the processors I have investigated are configured with a disabled CHA/SF/LLC slice at the same location as an enabled core.

Changing the number of enabled L3 slices would require a change in the hash function that maps addresses to the active slices.  (These mapping functions are discussed in  The selection of the mapping function might be fused into the chip at manufacturing time?

Changing the locations of enabled L3 slices would require a change in the routing tables that contain the physical locations of the logical L3 slice numbers.  These tables might be fused in at manufacturing time or constructed very early in the boot process (by confidential/secret/undocumented code).


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New Contributor I

Dear John,


Noted with thanks. 



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