Verilog conditional compilation: `defines and `ifdefs

[Altera_Forum]

There was a helpful thread (http://www.alteraforum.com/forum/showthread.php?t=1996) about configuring `defines in .qsf file. I use conditional compilation to optionally remove parts of code from compilation, usually for debugging purposes. I used it for some time but recently I've come across a little puzzle. 

 Suppose I have two files, top.v and foobar.v. top.v defines a module top that uses foobar defined in foobar.v. The code in foobar is braced by `ifdef USE_FOOBAR.  Now, the question is if i put `define USE_FOOBAR at the top of top.v, will it guarrantee that USE_FOOBAR will be defined when the compiler reaches foobar.v? It seems that it will not, but I can't figure out when it works and when it does not. I have a rather complex project where it definitely works and a pretty simple one where it doesn't, but I don't see a pattern.

[Altera_Forum]

Are you explicitly adding your source files to the project or do you expect QII to find them automatically? In a compile, once QII sees a `define, it will be visible to all Verilog source files that are analyzed (parsed) later. This is actually a rather nasty behavior that's defined by the IEEE standard. In SystemVerilog, there's a concept of a compilation unit that can break the global scope of `defines. In fact, the SV standard says that each file should be a unique compilation unit by default...or at least, each file compiled separately on the command line. I believe Modelsim switched to this behavior even when compiling pure Verilog designs.  

 Global defines are particularly troublesome for IP developers. A user can disable implicit net declarations with a compiler directive and thereby break the IP that relied on a perfectly legal (and totally insane) feature of the language.

[Altera_Forum]

I add files to the project explicitly. But until I can reproduce the problem again I can't add much more. I guess a better solution would be to put all defines in a separate config.h. 

 `default_nettype none is my first line in every .v file I create. I suffered terribly before I discovered this fantastic feature ;)

[Altera_Forum]

Quartus II caches elaborated netlists in the database. When you hit Play again, it re-uses them unless something relevant (a source file, a macro, etc.) makes them stale. Years ago, the software sometimes re-used a netlist when it shouldn't, but I haven't personally experienced or heard about similar problems in recent memory. Maybe because people simply wipe the database when anything inexplicable happens and get on with life. Were you changing the `define after having run a compile?  

 Post something if you manage to reproduce the problem!  Best of luck,  Josh

[Altera_Forum]

Okay Josh, thanks for the hint! I'm aware of the old "wipe the db if everything fails" trick but it didn't work for me that time. Of course I was changing the defines after several compile runs and it was QII-WE-7.1. Will write back when/if it happens again. I have over a year of experience with Verilog and Quartus but anyway every time something like this (0 LE's in module, go figure, stuck clock?) happens I tend to panic.

[Altera_Forum]

I reproduced the situation. Same example as I described.. Top-level entity is defined as top in settings, but in the Project Navigator, top.v is second after foobar.v. In this case, a `define from top.v has no effect on foobar.v, even though top.v is a top-level entity. I couldn't see often before because I tend to put top-level file with all my defines at the top of list just for aesthetical reasons. 

 My conclusion is that Quartus preprocesses files sequentially as they're listed in .qsf, ignoring the top-level definition as such. Makes sense, now that I think more about it.

[Altera_Forum]

i hav used `define under if loops..but even if the condition fails, it seems that `define s executed.. can anyone help me..my prob in hand is that, i need to execute the same module with different parameters according to the input condition

[Altera_Forum]

Your situation is slightly unclear, but it seems that you expect a pre-processor directive to be guarded by a conditional generate statement. Pre-processor directives are resolved during the parsing of the design file, whereas conditional generates are resolved during elaboration. You should use conditional generates completely in place of pre-processor directives, if possible.

[Altera_Forum]

but for generate the condition need to be a constant expression and cannot the inputs. i want the parameter 'p' of a sub-module to change as the input 'i' changes.