Different compiling results ModelSim <-> Quartus 9.0

[Altera_Forum]

Hi, 

 I have a VHDL Design containing a case statement. If I compile this design with QuartusII 9.0 I get no error; compiling this design in ModelSim Altera Starter Edition I get some errors like "Array type case expression must be of a locally static subtype" and "Case choice must be a locally static expression". I Think the reason is that I use a "generic expression" in the case-statement. Why did Quartus compile that without errors and ModelSim do not? The synthesized Design will work, but I will do the simulation as well. Any ideas to solve the problem? I attached the VHDL code...   Thanks for help!

[Altera_Forum]

--- Quote Start ---  I Think the reason is that I use a "generic expression" in the case-statement.  --- Quote End ---  Right. The solution is to avoid them for designs intended for ModelSim simulation. There are also some other cases where some expressions are tolerated with Quartus integrated synthesis but complained by ModelSim. According to the VHDL standard, only simple expressions are allowed in a case choices term. A shift operation isn't a simple expression. I guess, the best readable replacement is a chain of if then elsif.