Warnings in Quartus

[Altera_Forum]

I have a system in which I am attempting to run program code from sdram on a DE2 board. I get the following warnings after quartus compilation. 

 Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "SDRAM_cke" is stuck at VCC  The pin SDRAM_cke is connected directly to the corresponding output from the SOPC system.  Also, I am getting these warnings...  Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning: Found pins functioning as undefined clocks and/or memory enables Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details  When I check the the ignored assignments I see the following:  Fast Input Register sdram za_data[0] ON Compiler or HDL Assignment  There is an entry for each data bit on the sdram. When I check the ignored timing assignments I see this entry...  Cut Timing Path On * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module No timing path applicable to specified source and destination  When I try to run code I get the infamous verify failed message from the memory of my sdram. I have a PLL connected to the sdram clock pin with a -3ns phase shift. I am using the "e" version of the Nios 2 cpu. I have been struggling with this issue for some time. Any help would be appreciated  Chase

[Altera_Forum]

You read the warning : 

"Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "SDRAM_cke" is stuck at VCC"   Maybe this is exactly what you want. Did you put the SDRAM_cke signal stuck to '1' in order to permanently enable the SDRAM?   If so this is a warning that you can ignore.   Sorry but I cannot help for the rest.

[Altera_Forum]

Well if this is indeed what I want (not entirely sure because I don't have much experience with using SDRAM) then I did not set it this way explicitly. ALso, the warning came into my system after I added the SDRAM. When I first added the component, this warning was not there. It only came several compilations and changes later. 

 Thank you for your input. I can't see any direct consequences of any of these warnings.... I am basically looking for the reason why my code always fails when run from SDRAM.... The infamous verify failed message is killing me...

[Altera_Forum]

--- Quote Start ---  Well if this is indeed what I want (not entirely sure because I don't have much experience with using SDRAM) then I did not set it this way explicitly. ALso, the warning came into my system after I added the SDRAM. When I first added the component, this warning was not there. It only came several compilations and changes later.  Thank you for your input. I can't see any direct consequences of any of these warnings.... I am basically looking for the reason why my code always fails when run from SDRAM.... The infamous verify failed message is killing me...  --- Quote End ---    Hi,  some explanations about the other warnings:  warning: ignoring invalid fast i/o register assignments. see the ignored assignments panel in the fitter compilation report for more information. The assignment should force the Fitter to place the input FF in a FPGA I/O cells. The warning means that the FF could not implement in the I/O cell. Maybe it is worth to  look for the reason.   warning: found pins functioning as undefined clocks and/or memory enables Quartus found some signals which are used as Clock or Enable, but are not expressly defined as such.   cut timing path on * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module no timing path applicable to specified source and destination  This simply means that Quartus could not find a path. Check path name .  Kind regards  GPK