regarding reset address in flash

[Altera_Forum]

Hi all, 

 i am getting the following error when  i build the project    Post-processing to create cfi_flash.flash Oct 4, 2005 2:49:37 PM - (SEVERE) elf2flash: Boot copier overlaps data in flash Oct 4, 2005 2:49:37 PM - (SEVERE) elf2flash: Error generating Flash file, exiting make: *** [cfi_flash.flash] Error 5   i have set reset address and exception address in flash.  program,rom,r/w memory all set to SDRAM.  application is only hello world program. what does it mean? should i not have reset and exception address both in flash? can anybody suggest where am i doing wrong?  thanks in advance  regards prasad

[Altera_Forum]

Hi: 

 For booting from the CFI flash device, the tools insert a small boot code (see source at altera\kits\nios2\components\altera_nios2\sdk\src\boot_loader_sources in install directory) that copies your program from the CFI to ram.  If you place the exception address also in flash (which will surely be at offset 0x20 from flash start) the boot code will overlap with it.  Open the SOPCBuilder and change the exception address to ram (internal or external). This should solve your problem.  Setting reset address to flash and program (code/data/etc.) to ram will instruct the tools to generate the proper boot loader to relocate your code from flash to ram.

[Altera_Forum]

Hi VLorenzo 

But it should put only reset vector and exception vector at reset address and exception addresses no? why is it putting entire boot code. still i am unclear. actually it should put reset vector(jump to boot code) at reset address and exception vector(jump to exception service routine)  and then put boot loader before main of the program. please give me your views on this. regards prasad   residing some where    --- Quote Start ---  originally posted by vlorenzo@Oct 4 2005, 07:25 AM hi:  for booting from the cfi flash device, the tools insert a small boot code (see source at altera\kits\nios2\components\altera_nios2\sdk\src\boot_loader_sources in install directory) that copies your program from the cfi to ram.  if you place the exception address also in flash (which will surely be at offset 0x20 from flash start) the boot code will overlap with it.  open the sopcbuilder and change the exception address to ram (internal or external). this should solve your problem.  setting reset address to flash and program (code/data/etc.) to ram will instruct the tools to generate the proper boot loader to relocate your code from flash to ram. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10135)  --- quote end ---    --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  originally posted by prasad_forums@Oct 5 2005, 10:14 PM but it should put only reset vector and exception vector at reset address and exception addresses no?  --- Quote End ---   I see your confusion. You&#39;re thinking of other CPU architectures, where the CPU loads an address from a reset vector on startup into the PC and starts execution from there.  Nios2 doesn&#39;t do that. That reset address you put in SOPC builder is where it starts execution. No vector fetching. Nios2 doesn&#39;t even have a vector table; all exceptions result in the CPU state being saved and the processor jumping to the exception address.  So say you run entirely from flash at address 0x0. 0x0 through 0x1F contain a small bit of code that clears the instruction cache and jumps to _start. Address 0x20 is the start of the exception handler routine. _start is usally located somewhere after the exception handler routine.  Now say you boot from flash at 0x0 but run from SDRAM at 0x10000000. The flash contains a small bootloader which copies one or more data blocks from flash to SDRAM, then jumps to the _start address in SDRAM, and uses no RAM, just registers. The data to be copied to the SDRAM resides in the flash, immediately after this bootloader, and is followed by the SDRAM address of the _start routine. The SDRAM, after the bootloader is done, will contain the exception handler at 0x10000020, followed by the _start routine, followed by the rest of your code, then .rodata, then .rwdata, then .bss. SDRAM addresses 0x10000000 to 0x1000001F are unused.  How does it know which to do? It looks at whether or not your exception handler address is in volatile memory (e.g. SDRAM) or not (e.g. flash).

[Altera_Forum]

Hi Mike 

thank you very much for clearing my confusion. now the things are some what clear for me. i will work on this and i will mail if i need any help. thanks a lot prasad CRL-BEL, India

[Altera_Forum]

Hi Mike 

 will there be any problem if i set  both reset and exception address in flash and set the program and rom memories also in flash and only r/w memory in sdram? It should work no? then it that case should i program flash using flash programmer?  thanks and regards prasad

[Altera_Forum]

Hi prasad, 

 > i have set reset address and exception address in flash. >  > program,rom,r/w memory all set to SDRAM.  Read the Nios II Software Developer’s Handbook -- it&#39;s full of useful information.  Regards, --Scott

[Altera_Forum]

--- Quote Start ---  originally posted by prasad_forums+oct 7 2005, 04:26 am--><div class='quotetop'>quote (prasad_forums @ oct 7 2005, 04:26 am)</div>  --- quote start ---  will there be any problem if i set  both reset and exception address in flash and set the program and rom memories also in flash and only r/w memory in sdram?[/b]  --- quote end ---   that will work fine. slower, but fine.  <!--quotebegin-prasad_forums@Oct 7 2005, 04:26 AM then it that case should i program flash using flash programmer?  --- Quote End ---   That&#39;s a different topic... and I have to agree with smcnutt, you should look that up in the manual. There&#39;s no short answer. Pay special attention to the part about porting your custom board to the flash programmer (which may be in a separate tech note; look in your documents folder or on Altera&#39;s site).

[Altera_Forum]

Hi Mike  

Actually i am using NDB with Stratix II device i have set the reset address in flash and exception in sdram  1) prog and rom memory in flash and r/w memory in sdram  i have taken simple application only printf to the console.  i have programmed both .sof and application into flash using flash progammer   when i simply program the flash and press reset config switch   it is configurng the fpga and led is glowing .but when i press reset cpu switch   nothing is being printed onto the screen  then i tried run (with ""Reset the target and execute from reset vector (no download)" in the run menu it is just printing the following on the console "nios2-terminal: connected to hardware target using JTAG UART on cable  nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0  nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)"  so i am not understanding the things where they are going wrong. can u please me help me in this .  2) also if put prog/rom/r/w/ all memories in sdram and does the above   of programming flash and press switch i am not getting any output on the console  thanks and regards prasad  also small request can u please explain me the use  three options in the  Run menu and debugger(elf debugger) sub-menu 1) .download into RAM 2) attach to the existing program (no download) 3)""Reset the target and execute from reset vector (no download)"  i read the devloper hand book and nios IDE help regarding still it is not clear for me.  thanks in advance prasad

[Altera_Forum]

Regarding why your program won&#39;t print... I can&#39;t explain it; I&#39;d recreate the entire software project, if I faced that. Just in case something got messed up somewhere. 

   --- Quote Start ---  originally posted by prasad_forums@Oct 9 2005, 05:45 AM also small request can u please explain me the use  three options in the  run menu and debugger(elf debugger) sub-menu 1) .download into ram 2) attach to the existing program (no download) 3)""reset the target and execute from reset vector (no download)"   i read the devloper hand book and nios ide help regarding still it is not clear for me.  --- Quote End ---   These assume you have a debugger module in your CPU. 1) This does the following: - Attaches to the debug port via JYAG - Halt the processor - Copy the program (text/rodata/rwdata) to wherever they&#39;re supposed to be in RAM (NOTE: This won&#39;t work if the program is in flash). - Sets the PC to point to the start address of the new program. - Releases the CPU from the halt state. 2) This just attaches to the debug port via JTAG, so you can do things like set breakpoints and inspect memory. It assumes the program in question is already running on the target. 3) Does the same as 2) except it also tells the CPU (and maybe the whole SOPC system block) to reset itself.