Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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default values for signals

Altera_Forum
Honored Contributor II
‎10-20-2007 11:21 AM
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Hi all, 

 

Let's suppose in my FPGA design I have a simple synchronous binary counter which increments on every CLK rising edge. 

 

I have a reset pin that puts the latches in a known state (for example, if 4 bits counter: "0000"). 

 

If not physically reset, what will be the initial value for the counter?  

 

Is it "0000" or can it be undefined? How to specify default value for signals in quartus II? 

 

Thanks for your help 

 

Whitebird
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Altera_Forum
Honored Contributor II
‎10-20-2007 04:15 PM
299 Views

your counter will be 0 after fpga powered on.

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Altera_Forum
Honored Contributor II
‎10-20-2007 05:30 PM
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OK thanks alexandre. 0 is exactly what I want. 

 

Whitebird
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Altera_Forum
Honored Contributor II
‎10-22-2007 07:14 AM
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Quartus II help has a nice description on power-up state- you might want to take a look at the QII help using keywords "power-up state, specifying". 

 

- pakumpul
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Altera_Forum
Honored Contributor II
‎10-23-2007 10:37 PM
299 Views

OK thanks pakumpul 

 

Whitebird
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